2013 conference paper

Design of controller for L2 cache mapped in Tezzaron stacked DRAM

2013 IEEE International 3D Systems Integration Conference (3DIC). Presented at the 2013 IEEE International 3D Systems Integration Conference (3DIC), San Francisco, CA.

By: N. Tshibangu n, P. Franzon n , E. Rotenberg n & W. Davis n 

co-author countries: United States of America πŸ‡ΊπŸ‡Έ

Event: 2013 IEEE International 3D Systems Integration Conference (3DIC) at San Francisco, CA on October 2-4, 2013

Source: NC State University Libraries
Added: August 6, 2018

3DIC technology allows implementation of fast and dense memory by allowing multiple layers of DRAM to be fabricated in a single die called Die-stacking technology. This creates opportunity to explore usage of DRAM as fast last level cache by exploiting mapping of data and tag in the same bank. This Paper investigates the implementation of such a cache controller using 3-layer 256 MB Tezzaron Octopus stacked DRAM. This memory provides a fast data access through burst-4 and burst-8 mode. To avoid multiple row activation, the entire set is confined in one row of 2KB. For a 64B cache block, 32 lines of data can be obtained in one row. In this design, only two cache blocks are used for tag while 30 blocks are used for data yielding a 30-way set associative L2 cache. Given the performance of Tezzaron memory, a low hit time of approximately 20 cycles was achieved. This hit latency includes precharge and row activation delays. This access latency was used in Gem5 full-system simulator to estimate the performance compared to a standard 2D SRAM L2 cache. An average of 15% on performance is achieved on different benchmarks while providing an average 27% on energy saving.