2022 journal article

A General Multilevel Polygonal Space Vector Generation Scheme With Reduced Switching for the Inverter and Harmonic Suppression Using a Switched-Capacitive Filter for the Full Modulation Range

*IEEE Transactions on Power Electronics*, *37*(7), 8167–8176.

author keywords: Flying capacitor (FC); harmonic suppression; induction motor (IM) drives; multilevel inverters (MLIs); polygonal space vector structure; pulsewidth modulation (PWM)

Source: ORCID

Added: March 30, 2022

In this article, a general multilevel polygonal space vector generation scheme is proposed for open-end induction motor drive schemes, fed with any conventional multilevel inverter with active dc-link supply on one end and a low-voltage capacitor-fed inverter working as a switched-capacitive filter on the other end. The main power delivery primary inverter provides active power for motoring operation, and the capacitor-fed secondary switched-capacitive filter suppresses lower order harmonics by forming polygonal space vector structures of 36, 42, 48, etc., sides. In the proposed general modulation scheme, the primary inverter is visualized as a combination of subhexagons. Two subhexagons of the primary inverter are modulated in the pseudo six-step mode of operation to generate the desired fundamental component to drive the induction motor load. The primary inverter also generates undesirable lower order harmonics due to low switching per cycle in the primary inverter. The secondary inverter is used as a switched-capacitive filter to suppress the lower order harmonics of the 5th, 7th, 11th, 13th, etc., order by forming polygonal switching vectors with sides more than six, i.e., 36, 42, 48, etc. The proposed general scheme is verified for a three-level primary inverter fed with an active dc link of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$V_{\text{dc}}$</tex-math></inline-formula> and a six-level secondary inverter fed with a capacitive supply balanced at nearly one-third of the dc-link voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\text{0.39}V_{\text{dc}}$</tex-math></inline-formula> ).