2021 article

Design for 3D Stacked Circuits

2021 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM).

By: P. Franzon‚ÄČ, W. Davis, E. Rotenberg, J. Stevens, S. Lipa, T. Nigussie, H. Pan n, L. Baker ...

Source: Web Of Science
Added: July 11, 2022

2.5D and 3D technologies can give rise to a node equivalent of scaling due to improved connectivity. Aggressive exploitation scenarios include functional partitioning, circuit partitioning, logic on DRAM, design obfuscation and modular chiplets. Design issues that need to be addressed in pursuing such exploitations include thermal management, design for test and computer aided design.