Wentai Liu

Transparent arrays of bilayer-nanomesh microelectrodes for simultaneous electrophysiology and two-photon imaging in the brain

SCIENCE ADVANCES, 4(9).

Integrated circuit devices having on-chip adaptive bandwidth buses and related methods

Washington, DC: U.S. Patent and Trademark Office.

A low-power multirate differential PSK receiver for space applications

IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY, 54(6), 2074–2084.

Interpolating sense amplifier circuits and methods of operating the same

Washington, DC: U.S. Patent and Trademark Office.

A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 12(8), 876–880.

An arbitrary waveform stimulus circuit for visual prostheses using a low-area multibias DAC

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 38(10), 1679–1690.

Computed SAR and thermal elevation in a 0.25-mm 2-D model of the human eye and head in response to an implanted retinal stimulator - Part I: Models and methods

IEEE TRANSACTIONS ON ANTENNAS AND PROPAGATION, 51(9), 2274–2285.

Computed SAR and thermal elevation in a 0.25-mm 2-D model of the human eye and head in response to an implanted retinal stimulator - Part II: Results

IEEE TRANSACTIONS ON ANTENNAS AND PROPAGATION, 51(9), 2286–2295.

Electronic visual prosthesis

ARTIFICIAL ORGANS, 27(11), 986–995.

Raised cosine approximation signalling technique for reduced simultaneous switching noise

ELECTRONICS LETTERS, 38(21), 1256–1258.

Retinal prosthesis for the blind

Survey of Ophthalmology, 47(4), 335–356.

A neuro-stimulus chip with telemetry unit for retinal prosthetic device

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 35(10), 1487–1497.

Integrated circuits having cooperative ring oscillator clock circuits therein to minimize clock skew

Washington, DC: U.S. Patent and Trademark Office.

Integrated parametric timing optimization of digital systems

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 19(4), 482–489.

Convolution, deconvolution, and mean field annealing suitable for analog VLSI

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 46(2), 120–128.

Wave-pipelining: A tutorial and research survey

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 6(3), 464–474.

A CMOS high-speed data recovery circuit using the matched delay sampling technique

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 32(10), 1588–1596.

Clocking optimization and distribution in digital systems with scheduled skews

JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 16(2-3), 131–147.

Control of diamond heteroepitaxy on nickel by optical reflectance

APPLIED PHYSICS LETTERS, 70(22), 2960–2962.

The delay vernier pattern generation technique

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 32(4), 551–562.