Sumedh W. Sathaye

Conte, T. M., & Sathaye, S. (2000). Properties of rescheduling size invariance for dynamic rescheduling-based VLIW cross-generation compatibility. IEEE TRANSACTIONS ON COMPUTERS, 49(8), 814–825. https://doi.org/10.1109/12.868027

Conte, T. M., Menezes, K. N., Sathaye, S. W., & Toburen, M. C. (2000). System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 8(2), 129–137. https://doi.org/10.1109/92.831433

Banerjia, S., Sathaye, S. W., Menezes, K. N., & Conte, T. M. (1998). MPS: Miss-path scheduling for multiple-issue processors. IEEE TRANSACTIONS ON COMPUTERS, 47(12), 1382–1397. https://doi.org/10.1109/12.737684

Conte, T. M., & Sathaye, S. W. (1997, April). Optimization of VLIW compatibility systems employing dynamic rescheduling. INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING, Vol. 25, pp. 83–112. https://doi.org/10.1007/BF02700048