@article{ehrstein_richter_chandler-horowitz_vogel_young_shah_maher_foran_hung_diebold_2006, title={A comparison of thickness values for very thin SiO2 films by using ellipsometric, capacitance-voltage, and HRTEM measurements}, volume={153}, ISSN={["0013-4651"]}, DOI={10.1149/1.2133710}, abstractNote={A comparative study of very thin SiO 2 film thickness values obtained from the three dominant measurement techniques used in the integrated circuit industry, ellipsometry, capacitance-voltage (C-V) measurements, and transmission electron microscopy (TEM) has been completed. This work is directed at evaluating the metrology capabilities that might support the development of thickness reference materials for very thin dielectric films. We used a variety of models to analyze ellipsometry measurements and used three different quantum-mechanical-based algorithms to account for substrate quantized states and depletion effects in the polysilicon electrode to analyze the C-V results. TEM measurements were conducted by both phase contrast high resolution (HRTEM) and atomic number (Z) contrast high-angle annular dark-field scanning transmission electron microscopy (HAADF-STEM). We found a range of thickness values with each of the methods, with an overlap of values among the three techniques. HRTEM and STEM values showed less consistency between wafers than did ellipsometry or C-V, and seemed to be influenced more by local variations such as interface nonuniformities. We present sources of variation and estimates of the primary components of uncertainty for the measurements employed and discuss the implications of these results for obtaining consistent and unified film thickness metrology and for possible reference standards.}, number={1}, journal={JOURNAL OF THE ELECTROCHEMICAL SOCIETY}, author={Ehrstein, J and Richter, C and Chandler-Horowitz, D and Vogel, E and Young, C and Shah, S and Maher, D and Foran, B and Hung, PY and Diebold, A}, year={2006}, pages={F12–F19} }
 @article{suehle_vogel_roitman_conley_johnston_wang_bernstein_weintraub_2002, title={Observation of latent reliability degradation in ultrathin oxides after heavy-ion irradiation}, volume={80}, ISSN={["1077-3118"]}, DOI={10.1063/1.1448859}, abstractNote={Constant voltage time-dependent-dielectric-breakdown distributions were obtained for both unirradiated and irradiated 3.0 and 3.2 nm thick SiO2 films subjected to Co60 gamma irradiation and heavy ions of 823 MeV Xe129 (linear energy transfer=59 MeV-cm2/mg). The gamma irradiation had no effect on oxide lifetime. The heavy ion irradiation substantially reduced oxide life even though the devices were biased at 0.0 V during irradiation. The reduction of oxide lifetime under constant-voltage stress conditions was a strong function of the heavy ion fluence.}, number={7}, journal={APPLIED PHYSICS LETTERS}, author={Suehle, JS and Vogel, EM and Roitman, P and Conley, JF and Johnston, AH and Wang, B and Bernstein, JB and Weintraub, CE}, year={2002}, month={Feb}, pages={1282–1284} }
 @article{weintraub_vogel_hauser_yang_misra_wortman_ganem_masson_2001, title={Study of low-frequency charge pumping on thin stacked dielectrics}, volume={48}, ISSN={["1557-9646"]}, DOI={10.1109/16.974700}, abstractNote={The application of low-frequency charge pumping to obtain near-interface, or bulk trap densities, on thin stacked gate dielectrics is studied. A review of the theory governing the low-frequency charge pumping technique, developed to extract bulk trap densities from metal-oxide-semiconductor field-effect transistors (MOSFETs) fabricated with thick SiO/sub 2/ dielectrics, is given. In this study, the technique is applied to a series of n-channel MOSFETs fabricated with stacked gate dielectrics. The dielectric stacks were comprised of rapid thermal oxide (RTO) interface layers and rapid thermal chemical vapor deposited (RTCVD) oxynitride layers, which incorporated varying concentrations of nitrogen. The effect of DC tunneling currents on the technique is studied, and a procedure to remove these components from the measured substrate current is outlined. Distortions in the experimentally measured charge pumping current plotted as a function of gate bias is modeled and found to be due to the contribution of bulk traps. Finally, the limitations of applying a model that was originally developed for thick SiO/sub 2/ dielectrics to thin stacked gate dielectrics are discussed.}, number={12}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Weintraub, CE and Vogel, E and Hauser, JR and Yang, N and Misra, V and Wortman, JJ and Ganem, J and Masson, P}, year={2001}, month={Dec}, pages={2754–2762} }
 @article{henson_yang_kubicek_vogel_wortman_de meyer_naem_2000, title={Analysis of leakage currents and impact on off-state power consumption for CMOS technology in the 100-nm regime}, volume={47}, ISSN={["1557-9646"]}, DOI={10.1109/16.848282}, abstractNote={Off-state leakage currents have been investigated for sub-100 nm CMOS technology. The two leakage mechanisms investigated in this work include conventional off-state leakage due to short channel effects and gate leakage through ultrathin gate oxides. The conventional off-state leakage due to short channel effects exhibited the similar characteristics as previously published; however, gate leakage introduces two significant consequences with respect to off-state power consumption: (1) an increase in the number of transistors contributing to the total off-state power consumption of the chip and (2) an increase in the conventional off-state current due to gate leakage near the drain region of the device. Using experimentally measured data, it is estimated that gate leakage does not exceed the off-state specifications of the National Technology Roadmap for Semiconductors for gate oxides as thin as 1.4 to 1.5 nm for high performance CMOS. Low power and memory applications may be limited to an oxide thickness of 1.8 to 2.0 nm in order to minimize the off-state power consumption and maintain an acceptable level of charge retention. The analysis in this work suggests that reliability will probably limit silicon oxide scaling for high performance applications whereas gate leakage will limit gate oxide scaling for low power and memory applications.}, number={7}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Henson, WK and Yang, N and Kubicek, S and Vogel, EM and Wortman, JJ and De Meyer, K and Naem, A}, year={2000}, month={Jul}, pages={1393–1400} }
 @article{vogel_henson_richter_suehle_2000, title={Limitations of conductance to the measurement of the interface state density of MOS capacitors with tunneling gate dielectrics}, volume={47}, number={3}, journal={IEEE Transactions on Electron Devices}, author={Vogel, E. M. and Henson, W. K. and Richter, C. A. and Suehle, J. S.}, year={2000}, pages={601–608} }
 @article{masson_morfouli_autran_brini_balland_vogel_wortman_1999, title={Electrical properties of oxynitride thin films using noise and charge pumping measurements}, volume={245}, ISSN={["1873-4812"]}, DOI={10.1016/S0022-3093(98)00870-9}, abstractNote={Slow traps and interface traps density has been measured using low frequency (10 Hz) noise and charge pumping measurements. The study has been carried out on n-channel metal-oxide-semiconductor transistors with ultra thin gate dielectrics prepared by rapid thermal oxidation (RTO) and low pressure rapid thermal chemical vapor deposition. For both deposition methods, the interface trap characteristics have been studied as a function of nitrogen concentration as well as thermal annealing parameters (ambient and temperature). Experimental results have shown that a stacked dielectric combined RTO gate oxide (grown under N2O) and chemical vapor deposition oxynitride (capping layer with 8% atomic nitrogen concentration), offers a solution for gate dielectrics with thickness ⩾2 nm.}, journal={JOURNAL OF NON-CRYSTALLINE SOLIDS}, author={Masson, P and Morfouli, P and Autran, JL and Brini, J and Balland, B and Vogel, EM and Wortman, JJ}, year={1999}, month={Apr}, pages={54–58} }
 @article{henson_ahmed_vogel_hauser_wortman_venables_xu_venables_1999, title={Estimating oxide thickness of tunnel oxides down to 1.4 nm using conventional capacitance-voltage measurements on MOS capacitors}, volume={20}, ISSN={["0741-3106"]}, DOI={10.1109/55.753759}, abstractNote={High-frequency capacitance-voltage (C-V) measurements have been made on ultrathin oxide metal-oxide-semiconductor (MOS) capacitors. The sensitivity of extracted oxide thickness to series resistance and gate leakage is demonstrated. Guidelines are outlined for reliable and accurate estimation of oxide thickness from C-V measurements for oxides down to 1.4 nm.}, number={4}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Henson, WK and Ahmed, KZ and Vogel, EM and Hauser, JR and Wortman, JJ and Venables, RD and Xu, M and Venables, D}, year={1999}, month={Apr}, pages={179–181} }
 @article{shanware_massoud_vogel_henson_hauser_wortman_1999, title={Modeling the trends in valence-band electron tunneling in NMOSFETs with ultrathin SiO2 and SiO2/Ta2O5 dielectrics with oxide scaling}, volume={48}, ISSN={["1873-5568"]}, DOI={10.1016/s0167-9317(99)00392-5}, abstractNote={Gate oxide scaling in NMOSFETs causes electrons to tunnel from the conduction and valence bands of the silicon substrate in the direct-tunneling regime. In NMOSFETs, the tunneling of electrons from the substrate's valence band is a source of the substrate current IB and contributes to the gate current IG. Oxide thickness scaling leads to an increase in the substrate current IB and in the ratio IBIG of substrate to gate current. In this paper, we report the trends in the IBIG ratio due to oxide thickness scaling in ultrathin SiO2 and SiO2Ta2O5 composite gate dielectrics.}, number={1-4}, journal={MICROELECTRONIC ENGINEERING}, author={Shanware, A and Massoud, HZ and Vogel, E and Henson, K and Hauser, JR and Wortman, JJ}, year={1999}, month={Sep}, pages={295–298} }
 @article{li_mirabedini_vogel_henson_batchelor_wortman_kuehn_1998, title={Effects of Si source gases (SiH4 and Si2H6) on polycrystalline- Si1-xGex deposited on oxide by RTCVD}, volume={1}, number={3}, journal={Electrochemical and Solid State Letters}, author={Li, V. Z. Q. and Mirabedini, M. R. and Vogel, E. and Henson, K. and Batchelor, A. D. and Wortman, J. J. and Kuehn, R. T.}, year={1998}, pages={153–155} }
 @article{srivastava_heinisch_vogel_parker_osburn_masnari_wortman_hauser_1998, title={Evaluation of 2.0 nm grown and deposited dielectrics in 0.1 mu m PMOSFETs}, volume={525}, ISBN={["1-55899-431-9"]}, ISSN={["0272-9172"]}, DOI={10.1557/proc-525-163}, abstractNote={ABSTRACT}, journal={RAPID THERMAL AND INTEGRATED PROCESSING VII}, author={Srivastava, A and Heinisch, HH and Vogel, E and Parker, C and Osburn, CM and Masnari, NA and Wortman, JJ and Hauser, JR}, year={1998}, pages={163–170} }
 @article{vogel_ahmed_hornung_henson_mclarty_lucovsky_hauser_wortman_1998, title={Modeled tunnel currents for high dielectric constant dielectrics}, volume={45}, ISSN={["0018-9383"]}, DOI={10.1109/16.678572}, abstractNote={The effect of dielectric constant and barrier height on the WKB modeled tunnel currents of MOS capacitors with effective oxide thickness of 2.0 nm is described. We first present the WKB numerical model used to determine the tunneling currents. The results of this model indicate that alternative dielectrics with higher dielectric constants show lower tunneling currents than SiO/sub 2/ at expected operating voltages. The results of SiO/sub 2//alternative dielectric stacks indicate currents which are asymmetric with electric field direction. The tunneling current of these stacks at low biases decreases with decreasing SiO/sub 2/ thickness. Furthermore, as the dielectric constant of an insulator increased, the effect of a thin layer of SiO/sub 2/ on the current characteristics of the dielectric stack increases.}, number={6}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Vogel, EM and Ahmed, KZ and Hornung, B and Henson, WK and McLarty, PK and Lucovsky, G and Hauser, JR and Wortman, JJ}, year={1998}, month={Jun}, pages={1350–1355} }
 @article{morfouli_ghibaudo_vogel_hill_misra_mclarty_wortman_1997, title={Electrical and reliability properties of thin silicon oxinitride dielectrics formed by low pressure rapid thermal chemical vapor deposition}, volume={41}, ISSN={["0038-1101"]}, DOI={10.1016/S0038-1101(97)00019-1}, abstractNote={The electrical properties and reliability issues of MOSFETs with an ultra thin silicon oxinitride gate film (5 nm up to 8.5 nm), prepared by low pressure rapid thermal chemical vapor deposition are studied with the goal to evaluate the impact of the nitridation on the electrical properties of MOSFETs. More specifically, the wear-out and breakdown features of oxinitride dielectrics are investigated as a function of the nitrogen concentration in the film. The charge building up in the insulator bulk was evaluated while the interface reliability parameters were extracted from charge pumping and transfer characteristics measurements after constant current gate stress (1 mA cm−2). The optimum nitridation rate for minimizing the charge building up is shown to be 2–3%. However the charge-to-breakdown was found to decrease continuously after nitridation.}, number={7}, journal={SOLID-STATE ELECTRONICS}, author={Morfouli, P and Ghibaudo, G and Vogel, EM and Hill, WL and Misra, V and McLarty, PK and Wortman, JJ}, year={1997}, month={Jul}, pages={1051–1055} }