@article{lee_wu_lucovsky_2004, title={Breakdown and reliability of p-MOS devices with stacked RPECVD oxide/nitride gate dielectric under constant voltage stress}, volume={44}, ISSN={["0026-2714"]}, DOI={10.1016/j.microrel.2003.07.002}, abstractNote={In this work, the effects of voltage and temperature on the TDDB characteristics of ∼2.0 nm stacked oxide/nitride (O/N) dielectric, prepared by remote plasma enhanced CVD (RPECVD), has been investigated. The breakdown characteristics and time-to-breakdown (tBD) are recorded from p+-poly/n-Si capacitors under constant voltage stress (CVS) at different temperatures. The tBD cumulative distributions exhibit a single Weibull slope β of ∼1.9 for different applied voltages. The charge-to-breakdown (QBD) is integrated from the gate current as a function of stress times, and can be used to extract the defect generation rate. The activation energy of 0.39 eV is determined from the Arrhenius law, and the average temperature acceleration factor is about 45 between 25 and 125 °C for a constant gate voltage. The extrapolation of the TDDB lifetime with low percentile failure rate of 0.01% provides a 10-year projection for a total gate area of 0.1 cm2 on a chip at 125 °C with the Poisson area-scaling law and a constant voltage acceleration factor of ∼14.83 V−1. It is projected that the maximum safe operating voltage is ∼1.9 V for 2.07 nm O/N gate dielectric.}, number={2}, journal={MICROELECTRONICS RELIABILITY}, author={Lee, YM and Wu, YD and Lucovsky, G}, year={2004}, month={Feb}, pages={207–212} }
 @article{lee_wu_bae_hong_lucovsky_2003, title={Structural dependence of breakdown characteristics and electrical degradation in ultrathin RPECVD oxide/nitride gate dielectrics under constant voltage stress}, volume={47}, ISSN={["1879-2405"]}, DOI={10.1016/S0038-1101(02)00257-5}, abstractNote={Abstract The structural dependence of breakdown characteristics and electrical degradation in ultrathin oxide/nitride (O/N) dielectrics, prepared by remote plasma enhanced chemical vapor deposition, is investigated under constant voltage stress. In the early stage of oxide wearout, soft breakdown is a local phenomenon dominated by the tunneling current. After a given period of stress, a strong channel-length dependence of dielectric breakdown and the corresponding stress-induced leakage current from the evolution of increased tunneling current have been found. Stacked O/N dielectrics with interface nitridation demonstrate improved device performance on subthreshold swing and threshold voltage shifts after stress, indicating the suppression of stress-induced traps at the oxide/Si and oxide/drain interfaces compared to thermal oxides. Experimental evidence shows more severe breakdown and device degradation in the threshold voltage, drain current and transconductance for shorter channel PMOSFETs with O/N dielectrics. These degradations result from the enhancement of hole trapping in the gate–drain overlap region as evidenced by a positive off-state leakage current, which leads to hard breakdown, and the complete failure of device functionality.}, number={1}, journal={SOLID-STATE ELECTRONICS}, author={Lee, YM and Wu, YD and Bae, C and Hong, JG and Lucovsky, G}, year={2003}, month={Jan}, pages={71–76} }
 @article{wu_lee_lucovsky_2000, title={1.6 nm oxide equivalent gate dielectrics using nitride/oxide (N/O) composites prepared by RPECVD/oxidation process}, volume={21}, ISSN={["1558-0563"]}, DOI={10.1109/55.823574}, abstractNote={Ultrathin nitride/oxide (/spl sim/1.5/0.7 nm) dual layer gate dielectrics have been formed using remote plasma enhanced CVD of nitride onto plasma-grown oxide interface layers. High accumulation capacitance (1.72 /spl mu/F/cm/sup 2/) is measured and the equivalent oxide thickness is 1.6 nm after quantum effect corrections. Compared to 1.6 nm oxides, a tunneling current reduction of more than 100 fold is found for devices with 1.6 nm N/O dielectrics due to increased film thickness and interface nitridation. Hole channel mobility decreases by about 5%, yielding very good P-MOSFET current drive. Excellent dielectric reliability and interface robustness are also demonstrated for P-MOSFET's with N/O dielectrics.}, number={3}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Wu, YD and Lee, YM and Lucovsky, G}, year={2000}, month={Mar}, pages={116–118} }
 @article{wu_lucovsky_lee_2000, title={The performance and reliability of PMOSFET's with ultrathin silicon nitride/oxide stacked gate dielectrics with nitrided Si-SiO2 interfaces prepared by remote plasma enhanced CVD and post-deposition rapid thermal annealing}, volume={47}, ISSN={["1557-9646"]}, DOI={10.1109/16.848278}, abstractNote={Ultrathin (/spl sim/1.9 nm) nitride/oxide (N/O) dual layer gate dielectrics have been prepared by the remote plasma enhanced chemical vapor deposition (RPECVD) of Si/sub 3/N/sub 4/ onto oxides. Compared to PMOSFET's with heavily doped p/sup +/-poly-Si gates and oxide dielectrics, devices incorporating the RPECVD stacked nitrides display reduced tunneling current, effectively no boron penetration and improved interface characteristics. By preventing boron penetration into the bulk oxide and channel region, gate dielectric reliability and short channel effects are significantly improved. The hole mobility in devices with N/O dielectrics with equivalent oxide thickness between 1.8 nm and 3.0 nm is not significantly degraded. Because nitrogen is transported to the substrate/dielectric interface during post-deposition annealing, degradation of mobility during hot carrier stressing is significantly reduced for N/O devices. Compared with oxide, the tunneling current for N/O films with /spl sim/1.9 nm equivalent oxide thickness is lower by about an order of magnitude due to the larger physical thickness. Suppression of boron transport in nitride layers is explained by a percolation model in which boron transport is blocked in sufficiently thick nitrides, and is proportional to the oxide fraction in oxynitride alloys.}, number={7}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Wu, Y and Lucovsky, G and Lee, YM}, year={2000}, month={Jul}, pages={1361–1369} }
 @article{wu_xiang_yang_lucovsky_lin_2000, title={Time-dependent dielectric wearout technique with temperature effect for reliability test of ultrathin (< 2.0 nm) single layer and dual layer gate oxides}, volume={40}, ISSN={["0026-2714"]}, DOI={10.1016/s0026-2714(00)00103-7}, abstractNote={Ultrathin gate oxide is essential for low supply voltage and high drive current for ULSI devices. The continuous scaling of oxide thickness has been a challenge on reliability characterization with conventional time-dependent dielectric breakdown (TDDB) technique. A new technique, the time-dependent dielectric wearout (TDDW), is proposed as a more practical and effective way to measure oxide reliability and breakdown compared to conventional TDDB methodology. The wearout of oxide is defined as the gate current reaches a critical current density with the circuit operating voltage level. It is shown that although a noisy soft breakdown always exists for ultrathin oxide, with constant-voltage stressing, a big runaway can also be observed for oxides down to 1.8 nm by monitoring the I–V characteristics at a reduced voltage. Devices are found still working after soft breakdowns, but no longer functional after the big runaway. However, by applying E-model to project dielectric lifetime, it shows that the dielectric lifetime is almost infinity for the thermal oxide at 1.8 nm range. It is also demonstrated that the dual voltage TDDW technique is also able to monitor the breakdown mechanism for nitride/oxide (N/O) dual layer dielectrics.}, number={12}, journal={MICROELECTRONICS RELIABILITY}, author={Wu, YD and Xiang, Q and Yang, JYM and Lucovsky, G and Lin, MR}, year={2000}, month={Dec}, pages={1987–1995} }
 @article{lucovsky_wu_niimi_misra_phillips_1999, title={Bonding constraints and defect formation at interfaces between crystalline silicon and advanced single layer and composite gate dielectrics}, volume={74}, ISSN={["1077-3118"]}, DOI={10.1063/1.123728}, abstractNote={An increasingly important issue in semiconductor device physics is understanding of how departures from ideal bonding at silicon–dielectric interfaces generate electrically active defects that limit performance and reliability. Building on previously established criteria for formation of low defect density glasses, constraint theory is extended to crystalline silicon–dielectric interfaces that go beyond Si–SiO2 through development of a model that quantifies average bonding coordination at these interfaces. This extension is validated by application to interfaces between Si and stacked silicon oxide/nitride dielectrics demonstrating that as in bulk glasses and thin films, an average coordination, Nav, greater than three yields increasing defective interfaces.}, number={14}, journal={APPLIED PHYSICS LETTERS}, author={Lucovsky, G and Wu, Y and Niimi, H and Misra, V and Phillips, JC}, year={1999}, month={Apr}, pages={2005–2007} }
 @article{wu_xiang_bang_lucovsky_lin_1999, title={Time dependent dielectric wearout (TDDW) technique for reliability of ultrathin gate oxides}, volume={20}, ISSN={["0741-3106"]}, DOI={10.1109/55.767092}, abstractNote={The degradation of ultrathin oxides is measured and characterized by the dual voltage time dependent dielectric wearout (TDDW) technique. Compared to the conventional time-dependent dielectric breakdown (TDDB) technique, a distinct breakdown can be determined at the operating voltage I-t curve. A noisy, soft prebreakdown effect occurs for 1.8-2.7 nm ultrathin oxides at earlier stress times. The different stages of wearout of 1.8-2.7 nm oxides are discussed. The wearout of oxide is defined when the gate current reaches a critical current density at the circuit operating voltage. Devices still function after the soft breakdowns occur, but are not functional after the sharp breakdown. However, application of the E model to project the dielectric lifetime shows that this is more than 20 y for thermal oxides in the ultrathin regime down to 1.8 nm.}, number={6}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Wu, YD and Xiang, Q and Bang, D and Lucovsky, G and Lin, MR}, year={1999}, month={Jun}, pages={262–264} }
 @article{lucovsky_niimi_wu_parker_hauser_1998, title={Optimization of nitrided gate dielectrics by plasma-assisted and rapid thermal processing}, volume={16}, ISSN={["0734-2101"]}, DOI={10.1116/1.581291}, abstractNote={This article addresses several aspects of nitrogen atom (N atom) incorporation into ultrathin gate oxides including: (i) monolayer incorporation of N atoms at the Si–SiO2 interfaces to reduce tunneling currents and improve device reliability; and (ii) the incorporation of silicon nitride films into stacked oxide–nitride (ON) gate dielectrics to (a) increase the capacitance in ultrathin dielectrics without decreasing film thickness, and (b) suppress boron atom (B atom) diffusion from p+ polycrystalline Si gate electrodes through the dielectric layer to the Si substrate channel region. The results of this article demonstrate that these N-atom spatial distributions can be accomplished by low thermal budget, single wafer processing which includes (i) low-temperature (300 °C) plasma assisted oxidation, nitridation, and/or deposition to achieve the desired N-atom incorporation, followed by (ii) low thermal budget (30 s at 900 °C) rapid thermal annealing to promote chemical and structural bulk and interface relaxation.}, number={3}, journal={JOURNAL OF VACUUM SCIENCE & TECHNOLOGY A}, author={Lucovsky, G and Niimi, H and Wu, Y and Parker, CR and Hauser, JR}, year={1998}, pages={1721–1729} }
 @article{wu_lucovsky_1998, title={Ultrathin nitride/oxide (N/O) gate dielectrics for p(+)-polysilicon gated PMOSFET's prepared by a combined remote plasma enhanced CVD thermal oxidation process}, volume={19}, ISSN={["1558-0563"]}, DOI={10.1109/55.720188}, abstractNote={Ultrathin nitride-oxide (N/O/spl sim/1.5/2.6 nm) dual layer gate dielectrics have been incorporated into PMOSFETs with boron-implanted polysilicon gates. Boron penetration is effectively suppressed by the top plasma-deposited nitride layer leading to improved short channel performance as compared to PMOSFETs with oxide dielectrics. In addition, improved interface characteristics and hot carrier degradation immunity are also demonstrated for the devices with the N/O dual layer gate dielectrics.}, number={10}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Wu, YD and Lucovsky, G}, year={1998}, month={Oct}, pages={367–369} }