@article{williams_hulfachor_kim_littlejohn_holton_1998, title={Scaling trends for device performance and reliability in channel-engineered n-MOSFETs}, volume={45}, ISSN={0018-9383}, url={http://dx.doi.org/10.1109/16.658839}, DOI={10.1109/16.658839}, abstractNote={Channel-engineered MOSFETs with retrograde doping profiles are expected to provide increased carrier mobility and immunity to short channel effects. However, the physical mechanisms responsible for device performance of retrograde designs in the deep-submicron regime are not fully understood, and general device scaling trends are not well documented. Also, little effort has been devoted to the study of hot-electron-induced device degradation. In this paper, we employ a comprehensive simulation methodology to investigate scaling and device performance trends in channel-engineered n-MOSFETs. The method features an advanced ensemble Monte Carlo device simulator to extract hot-carrier reliability for super-steep-retrograde and more conventional silicon n-MOS designs with effective channel lengths scaled from 800 to 100 nm. With decreasing channel length, our simulations indicate that the retrograde design shows increasingly less total hot-electron injection into the oxide than the conventional design. However, near the 100-nm regime, the retrograde design provides less current drive, loses its advantage of higher carrier mobility, and exhibits much greater sensitivity to hot-electron-induced interface states when compared to the conventional device.}, number={1}, journal={IEEE Transactions on Electron Devices}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Williams, S.C. and Hulfachor, R.B. and Kim, K.W. and Littlejohn, M.A. and Holton, W.C.}, year={1998}, pages={254–260} }
 @article{hulfachor_kim_littlejohn_osburn_1997, title={Effects of silicon layer properties on device reliability for 0.1-μm SOI n-MOSFET design strategies}, volume={44}, ISSN={0018-9383}, url={http://dx.doi.org/10.1109/16.568044}, DOI={10.1109/16.568044}, abstractNote={We employ an advanced simulation method to investigate the effects of silicon layer properties on hot-electron-induced reliability for two 0.1-/spl mu/m SOI n-MOSFET design strategies. The simulation approach features a Monte Carlo device simulator in conjunction with commercially available process and device simulators. The two channel designs are: 1) a lightly-doped (10/sup 16/ cm/sup -3/) channel and 2) a heavily-doped (10/sup 18/ cm/sup -3/) channel. For each design, the silicon layer thicknesses (T/sub Si/) of 30, 60, and 90 nm are considered. The devices are biased under low-voltage conditions where the drain voltage is considerably less than the Si/SiO/sub 2/ barrier height for electron injection. A comparative analysis of the Monte Carlo simulation results shows that an increase in T/sub Si/ results in decreasing hot electron injection into the back oxide in both device designs. However, electron injection into the front oxide exhibits opposite trends of increasing injection for the heavily-doped channel design and decreasing injection for the lightly-doped channel design. These important trends are attributed to highly two-dimensional electric field and current density distributions. Simulations also show that the lightly-doped channel design is about three times more reliable for thick silicon layers. However, as the silicon layer is thinned to 30 nm, the heavily-doped channel design becomes about 10% more reliable instead.}, number={5}, journal={IEEE Transactions on Electron Devices}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Hulfachor, R.B. and Kim, K.W. and Littlejohn, M.A. and Osburn, C.M.}, year={1997}, month={May}, pages={815–821} }
 @article{tian_hulfachor_ellis-monaghan_kim_littlejohn_hauser_masnari_1994, title={An evaluation of super-steep-retrograde channel doping for deep-submicron MOSFET applications}, volume={41}, ISSN={0018-9383}, url={http://dx.doi.org/10.1109/16.324605}, DOI={10.1109/16.324605}, abstractNote={Performance and reliability of deep-submicron MOSFET's employing super-steep-retrograde (SSR) channel doping configurations are examined using self-consistent Monte Carlo and drift-diffusion simulations. It is found that SSR channel doped MOSFET's provide increased current drive and reduced threshold voltage shift when compared with conventional MOSFET structures. However, they also display a relatively higher substrate current and interface state generation rate. The physical mechanisms of performance enhancement/degradation and design tradeoffs for SSR channel doped MOSFET's are discussed. >}, number={10}, journal={IEEE Transactions on Electron Devices}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Tian, H. and Hulfachor, R.B. and Ellis-Monaghan, J.J. and Kim, K.W. and Littlejohn, M.A. and Hauser, J.R. and Masnari, N.A.}, year={1994}, pages={1880–1882} }