@article{park_fan_wang_huang_2010, title={A Sample-Data Model for Double Edge Current Programmed Mode Control (DECPM) in High-Frequency and Wide-Range DC-DC Converters}, volume={25}, ISSN={["1941-0107"]}, DOI={10.1109/tpel.2009.2036618}, abstractNote={This paper focuses on a sample-data model for double edge current programmed mode control (DECPM) and its application to high-frequency and wide-range dc-dc converters. Steady-state conditions and subharmonic oscillation issues for DECPM are addressed. By combining the conventional peak and valley current programmed mode control, a sample-data model for DECPM is proposed. A small signal model for DECPM is developed by deriving the modulation gains (Fm) and the sampling gains (He) for DECPM from the proposed sample-data model. The sampling frequency dependence on the duty ratio and a large current loop gain at high frequency for DECPM are emphasized. The analytical results are verified by the simulation. Finally, DECPM is proposed as a method to control the high-frequency and wide-range dc-dc converters. A 10-MHz four-switch buck boost converter is implemented with DECPM to verify the viability of its application to high-frequency and wide-range converters.}, number={4}, journal={IEEE TRANSACTIONS ON POWER ELECTRONICS}, author={Park, Jinseok and Fan, Jiwei and Wang, Xiaopeng and Huang, Alex}, year={2010}, month={Apr}, pages={1023–1033} }
 @article{lim_fan_huang_2010, title={Transient-voltage-clamp circuit design based on constant load line impedance for voltage regulator module}, volume={57}, DOI={10.1109/tie.2010.2042419}, abstractNote={A transient-voltage-clamp (TVC) circuit acts as a replacement of bulk capacitors, which is required for voltage regulator (VR) module (VRM) to clamp output voltage spikes. With the TVC circuit, VRM size is greatly reduced with similar transient performance. This paper presents a new TVC circuit. This TVC circuit is designed based on the constant load line impedance which is recently given by Intel's VRM11.0. The TVC circuit works in parallel with VR decoupling capacitors to achieve faster voltage regulation. The impedances of the VR, output capacitors, and the proposed TVC circuit are analyzed. The TVC circuit design procedure is described, and the transient performance and power consumption are discussed. The theoretical analysis is verified by simulation results. Moreover, the proposed TVC circuit is fabricated with a 0.6-μm CMOS process, and experimental results verify the simulation results and theoretical analysis.}, number={12}, journal={IEEE Transactions on Industrial Electronics}, author={Lim, S. and Fan, J. W. and Huang, A. Q.}, year={2010}, pages={4085–4094} }
 @inproceedings{fan_zhou_yang_huang_2009, title={A low power high noise immunity boost DC-DC converter using the differential difference amplifiers}, DOI={10.1145/1594233.1594249}, abstractNote={A new boost converter using the differential difference amplifiers (DDAs) in the control loop is proposed. Compared with the traditional current mode boost converters, the circuitry of this controller is much simpler and consumes less power by eliminating the loop compensation, current sensing, and slope compensation circuits. A large duty ripple voltage generated by an Rr-Cr network is compared with the DDAs' outputs to get the duty cycles and changes the boost converter from a second order to a first order system. The large noise margin of the duty ripple voltage also gives this control excellent noise immunity performance.}, booktitle={ISLPED 09}, author={Fan, J. W. and Zhou, X. and Yang, L. Y. and Huang, A.}, year={2009}, pages={63–68} }
 @inproceedings{yang_fan_huang_2009, title={Controller design issues and solutions for buck converters with phase shedding and AVP functions}, DOI={10.1109/ecce.2009.5316266}, abstractNote={For buck converters with high output current, multi-phase interleaving is popular. To improve light load efficiency, some phases can be shut down at light load. This is called phase shedding. Adaptive Voltage Positioning (AVP) is normally another requirement for high output current buck. Previous papers provided AVP design guidelines for buck converters without phase shedding. With phase shedding, are these design guidelines still valid? How to design the controller so that the output transient response doesn't get worse? This paper points out the controller design issues for buck converters with phase shedding and AVP. It is shown that the output will have worse transient response if the controller is designed in the same way as without phase shedding. New design guidelines are developed in this paper to solve the problem, which are verified by simulation and experimental results.}, booktitle={2009 IEEE Energy Conversion Congress and Exposition, Vols 1-6}, author={Yang, L. Y. and Fan, J. W. and Huang, A. Q.}, year={2009}, pages={2335–2341} }
 @article{fan_li_lim_huang_2009, title={Design and characterization of differentially enhanced duty ripple control (DE-DRC) for step-down converter}, volume={24}, DOI={10.1109/TPEL.2009.2028889}, abstractNote={A new control method, differentially enhanced duty ripple control (DE-DRC), is proposed for step-down converters. The control method uses a differentially enhanced loop to amplify the output error with positive and negative differential difference amplifiers (DDAs), and a duty ripple loop to include the input voltage and the duty cycle information into the control scheme. The duty ripple loop generates a very large control ripple voltage, and the control ripple is compared with a negative control voltage to trigger an on-pulse generator to get the duty cycle. Because of the large duty ripple voltage with a big noise margin and the low pass filter effect of DDAs, the proposed DE-DRC can achieve good noise immunity. The easily configured positive and negative DDA gains can separately adjust the high and low frequency portion of the loop transfer function, and push the control bandwidth to high frequency to achieve fast transient response. Because of a unique first-order character of the inner duty ripple loop, this control can also completely eliminate the double pole peaking from the output impedance and achieve ideal closed loop output impedance in the control bandwidth, which is preferred for adaptive voltage position designs.}, number={12}, journal={IEEE Transactions on Power Electronics}, author={Fan, J. W. and Li, X. N. and Lim, S. and Huang, A. Q.}, year={2009}, pages={2714–2725} }
 @inproceedings{zhou_fan_huang_2009, title={Monolithic DC offset self-calibration method for adaptive on-time control buck converter}, DOI={10.1109/ecce.2009.5316520}, abstractNote={In this paper, a monolithic self-calibration method is proposed to reduce DC offset of output voltage in buck converter with adaptive on-time control. The calibration system senses the average output voltage of converter and dynamically reduces offset by digital tuning the comparing reference. DC offset at output voltage caused by parasitic ESR, ESL of filter capacitor and loop delay can be effectively calibrated. The proposed calibration method doesn't impact fast transient response of the converter. Moreover, the calibration system can also be generally used to reduce output voltage DC offset of converter with bang-bang control.}, booktitle={2009 IEEE Energy Conversion Congress and Exposition, Vols 1-6}, author={Zhou, X. and Fan, J. W. and Huang, A.}, year={2009}, pages={176–179} }