@article{ahmed_wortman_hauser_2000, title={A two-dimensional numerical simulation of pulsed drain current transients in weak inversion and application to interface trap characterization on small geometry MOSFETs with ultrathin oxides}, volume={47}, ISSN={["0018-9383"]}, DOI={10.1109/16.877189}, abstractNote={Based on two-dimensional (2-D) numerical simulation, a pulsed-drain current (PDC) measurement technique in weak inversion is investigated as an alternative to the standard charge-pumping technique for the extraction of interface trap density using small geometry MOSFETs. The PDC technique was found particularly useful for small MOSFETs with sub-20 /spl Aring/ oxides to avoid high gate tunneling current effects. The numerical simulation results are in excellent agreement with the simple analytical expressions used in the PDC technique.}, number={11}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Ahmed, K and Wortman, JJ and Hauser, JR}, year={2000}, month={Nov}, pages={2236–2237} }
 @article{ahmed_ibok_hauser_2000, title={Analytic model of parasitic capacitance attenuation in CMOS devices with hyper-thin oxides}, volume={36}, ISSN={["1350-911X"]}, DOI={10.1049/el:20001160}, abstractNote={The parasitic accumulation capacitance attenuation in MOS structures with hyper-thin oxides has been modelled using a distributed RC network. The simple analytic model is in excellent agreement with a two-dimensional numerical simulation and experimental data.}, number={20}, journal={ELECTRONICS LETTERS}, author={Ahmed, K and Ibok, E and Hauser, J}, year={2000}, month={Sep}, pages={1699–1700} }
 @article{ahmed_ibok_bains_chi_ogle_wortman_hauser_2000, title={Comparative physical and electrical metrology of ultrathin oxides in the 6 to 1.5 nm regime}, volume={47}, ISSN={["0018-9383"]}, DOI={10.1109/16.848276}, abstractNote={In this work, five methods for measuring the thickness of ultra-thin gate oxide layers in MOS structures were compared experimentally on n/sup +/ poly-SiO/sub 2/-p-Si structures. Three methods are based on electrical capacitance-voltage (C-V) and current-voltage (I-V) data and the other two methods are HRTEM and optical measurement. MOS capacitors with oxide thickness in the range 17-55 /spl Aring/ have been used in this study. We found that thickness extracted using QM C-V and HRTEM agree within 1.0 /spl Aring/ over the whole thickness range when a dielectric constant of 3.9 was used. Comparison between thickness extracted using quantum interference (QI) I-V technique and optical measurement were also within 1.0 /spl Aring/ for thickness 31-47 /spl Aring/. However, optical oxide thickness was consistently lower than the TEM thickness by about 2 /spl Aring/ over the thickness range under consideration. Both optical measurement and QM C-V modeling yield the same thickness as the nominal oxide thickness increases (>50 /spl Aring/).}, number={7}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Ahmed, K and Ibok, E and Bains, G and Chi, D and Ogle, B and Wortman, JJ and Hauser, JR}, year={2000}, month={Jul}, pages={1349–1354} }
 @article{ahmed_de_osburn_wortman_hauser_2000, title={Limitations of the modified shift-and-ratio technique for extraction of the bias dependence of L-eff and R-sd of LDD MOSFET's}, volume={47}, ISSN={["0018-9383"]}, DOI={10.1109/16.831010}, abstractNote={The purpose of this study, based on two-dimensional (2-D) simulation, was to scale effective channel length and series resistance extraction routines for sub-100 nm CMOS devices. We demonstrate that L/sub eff/- and R/sub sd/-gate-bias dependence extracted using a modified shift-and-ratio (M-S&R) method may not give accurate results because of a nonnegligible effective mobility dependence on gate bias. Using a reasonable gate bias-dependent mobility model, one observes a finite V/sub g/ dependence of L/sub eff/ and R/sub sd/ even for devices with degenerately doped drain junction.}, number={4}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Ahmed, K and De, I and Osburn, C and Wortman, J and Hauser, J}, year={2000}, month={Apr}, pages={891–895} }
 @article{henson_ahmed_vogel_hauser_wortman_venables_xu_venables_1999, title={Estimating oxide thickness of tunnel oxides down to 1.4 nm using conventional capacitance-voltage measurements on MOS capacitors}, volume={20}, ISSN={["0741-3106"]}, DOI={10.1109/55.753759}, abstractNote={High-frequency capacitance-voltage (C-V) measurements have been made on ultrathin oxide metal-oxide-semiconductor (MOS) capacitors. The sensitivity of extracted oxide thickness to series resistance and gate leakage is demonstrated. Guidelines are outlined for reliable and accurate estimation of oxide thickness from C-V measurements for oxides down to 1.4 nm.}, number={4}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Henson, WK and Ahmed, KZ and Vogel, EM and Hauser, JR and Wortman, JJ and Venables, RD and Xu, M and Venables, D}, year={1999}, month={Apr}, pages={179–181} }
 @article{ahmed_ibok_yeap_xiang_ogle_wortman_hauser_1999, title={Impact of tunnel currents and channel resistance on the characterization of channel inversion layer charge and polysilicon-gate depletion of sub-20-angstrom gate oxide MOSFET's}, volume={46}, ISSN={["0018-9383"]}, DOI={10.1109/16.777153}, abstractNote={This paper discusses the limitations on MOSFET test structures used in extracting the polysilicon gate doping from capacitance-voltage (C-V) analysis in strong inversion, especially for ultrathin gate oxides. It is shown that for sub-20-/spl Aring/ oxide MOS devices, transistors with channel lengths less than about 10 /spl mu/m will be needed to avoid an extrinsic capacitance roll-off in strong inversion. The upper limit of the channel length has been estimated using a new simple transmission-line-model of the terminal capacitance, which accounts for the nonnegligible gate tunneling current and finite channel resistance.}, number={8}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Ahmed, K and Ibok, E and Yeap, GCF and Xiang, Q and Ogle, B and Wortman, JJ and Hauser, JR}, year={1999}, month={Aug}, pages={1650–1655} }
 @article{vogel_ahmed_hornung_henson_mclarty_lucovsky_hauser_wortman_1998, title={Modeled tunnel currents for high dielectric constant dielectrics}, volume={45}, ISSN={["0018-9383"]}, DOI={10.1109/16.678572}, abstractNote={The effect of dielectric constant and barrier height on the WKB modeled tunnel currents of MOS capacitors with effective oxide thickness of 2.0 nm is described. We first present the WKB numerical model used to determine the tunneling currents. The results of this model indicate that alternative dielectrics with higher dielectric constants show lower tunneling currents than SiO/sub 2/ at expected operating voltages. The results of SiO/sub 2//alternative dielectric stacks indicate currents which are asymmetric with electric field direction. The tunneling current of these stacks at low biases decreases with decreasing SiO/sub 2/ thickness. Furthermore, as the dielectric constant of an insulator increased, the effect of a thin layer of SiO/sub 2/ on the current characteristics of the dielectric stack increases.}, number={6}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Vogel, EM and Ahmed, KZ and Hornung, B and Henson, WK and McLarty, PK and Lucovsky, G and Hauser, JR and Wortman, JJ}, year={1998}, month={Jun}, pages={1350–1355} }