James Joseph Chambers

Method for controlling defects in gate dielectrics

Washington, DC: U.S. Patent and Trademark Office.

Refractory metal-based electrodes for work function setting in semiconductor devices

Washington, DC: U.S. Patent and Trademark Office.

Methods and systems to mitigate etch stop clipping for shallow trench isolation fabrication

Washington, DC: U.S. Patent and Trademark Office.

Process for manufacturing dual work function metal gates in a microelectronics device

Washington, DC: U.S. Patent and Trademark Office.

Reliable high voltage gate dielectric layers using a dual nitridation process

Washington, DC: U.S. Patent and Trademark Office.

High-K gate dielectric defect gettering using dopants

Washington, DC: U.S. Patent and Trademark Office.

Hydrogen free integration of high-k gate dielectrics

Washington, DC: U.S. Patent and Trademark Office.

Method for fabricating transistor gate structures and gate dielectrics thereof

Washington, DC: U.S. Patent and Trademark Office.

Refractory metal-based electrodes for work function setting in semiconductor devices

Washington, DC: U.S. Patent and Trademark Office.

Structure and method to fabricate self-aligned transistors with dual work function metal gate electrodes

Washington, DC: U.S. Patent and Trademark Office.

Top surface roughness reduction of high-k dielectric materials using plasma based processes

Washington, DC: U.S. Patent and Trademark Office.

Use of indium to define work function of p-type doped polysilicon

Washington, DC: U.S. Patent and Trademark Office.

Versatile system for triple-gated transistors with engineered corners

Washington, DC: U.S. Patent and Trademark Office.

High temperature interface layer growth for high-k gate dielectric

Washington, DC: U.S. Patent and Trademark Office.

Metal gate MOS transistors and methods for making the same

Washington, DC: U.S. Patent and Trademark Office.

Method for fabricating split gate transistor device having high-k dielectrics

Washington, DC: U.S. Patent and Trademark Office.

Versatile system for triple-gated transistors with engineered corners

Washington, DC: U.S. Patent and Trademark Office.

High-k gate dielectric with uniform nitrogen profile and methods for making the same

Washington, DC: U.S. Patent and Trademark Office.

Method for annealing ultra-thin, high quality gate oxide layers using oxidizer/hydrogen mixtures

Washington, DC: U.S. Patent and Trademark Office.

Use of indium to define work function of p-type doped polysilicon

Washington, DC: U.S. Patent and Trademark Office.

High dielectric constant metal silicates formed by controlled metal-surface reactions

Washington, DC: U.S. Patent and Trademark Office.

Temperature spike for uniform nitridization of ultra-thin silicon dioxide layers in transistor gates

Washington, DC: U.S. Patent and Trademark Office.

Effects of surface pretreatments on interface structure during formation of ultra-thin yttrium silicate dielectric films on silicon

APPLIED SURFACE SCIENCE, 181(1-2), 78–93.

Physical and electrical characterization of ultrathin yttrium silicate insulators on silicon

JOURNAL OF APPLIED PHYSICS, 90(2), 918–933.

Yttrium silicate formation on silicon: Effect of silicon preoxidation and nitridation on interface reaction kinetics

APPLIED PHYSICS LETTERS, 77(15), 2385–2387.

Endpoint uniformity sensing and analysis in silicon dioxide plasma etching using in situ mass spectrometry

JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 16(6), 2996–3002.