James Joseph Chambers

Colombo, L., Chambers, J. J., Visokay, M. R., & Rotondo, A. L. (2008). Method for controlling defects in gate dielectrics. Washington, DC: U.S. Patent and Trademark Office.

Colombo, L., Chambers, J. J., & Visokay, M. R. (2008). Refractory metal-based electrodes for work function setting in semiconductor devices. Washington, DC: U.S. Patent and Trademark Office.

Quevedo-Lopez, M., Chambers, J. J., & Olsen, L. C. (2007). Methods and systems to mitigate etch stop clipping for shallow trench isolation fabrication. Washington, DC: U.S. Patent and Trademark Office.

Colombo, L., Chambers, J. J., & Visokay, M. R. (2007). Process for manufacturing dual work function metal gates in a microelectronics device. Washington, DC: U.S. Patent and Trademark Office.

Khamankar, R., Grider, D. T., Niimi, H., Gurba, A., Tran, T., & Chambers, J. J. (2007). Reliable high voltage gate dielectric layers using a dual nitridation process. Washington, DC: U.S. Patent and Trademark Office.

Colombo, L., Chambers, J. J., & Rotondaro, A. L. (2006). High-K gate dielectric defect gettering using dopants. Washington, DC: U.S. Patent and Trademark Office.

Colombo, L., Chambers, J. J., & Visokay, M. R. (2006). Hydrogen free integration of high-k gate dielectrics. Washington, DC: U.S. Patent and Trademark Office.

Visokay, M. R., Colombo, L., Chambers, J. J., Rotondaro, A. L., & Bu, H. (2006). Method for fabricating transistor gate structures and gate dielectrics thereof. Washington, DC: U.S. Patent and Trademark Office.

Rotondaro, A. L., Chambers, J. J., & Jain, A. (2006). Refractory metal-based electrodes for work function setting in semiconductor devices. Washington, DC: U.S. Patent and Trademark Office.

Chambers, J. J. (2006). Structure and method to fabricate self-aligned transistors with dual work function metal gate electrodes. Washington, DC: U.S. Patent and Trademark Office.

Quevedo-Lopez, M. A., Chambers, J. J., Colombo, L., & Visokay, M. R. (2006). Top surface roughness reduction of high-k dielectric materials using plasma based processes. Washington, DC: U.S. Patent and Trademark Office.

Colombo, L., Chambers, J. J., & Rotondaro, A. L. (2006). Use of indium to define work function of p-type doped polysilicon. Washington, DC: U.S. Patent and Trademark Office.

Visokay, M. R., & Chambers, J. J. (2006). Versatile system for triple-gated transistors with engineered corners. Washington, DC: U.S. Patent and Trademark Office.

Colombo, L., Chambers, J. J., Rotondaro, A. L., & Visokay, M. R. (2005). High temperature interface layer growth for high-k gate dielectric. Washington, DC: U.S. Patent and Trademark Office.

Visokay, M. R., Colombo, L., & Chambers, J. J. (2005). Metal gate MOS transistors and methods for making the same. Washington, DC: U.S. Patent and Trademark Office.

Rotondaro, A. L., Visokay, M. R., Chambers, J. J., & Colombo, L. (2005). Method for fabricating split gate transistor device having high-k dielectrics. Washington, DC: U.S. Patent and Trademark Office.

Visokay, M. R., & Chambers, J. J. (2005). Versatile system for triple-gated transistors with engineered corners. Washington, DC: U.S. Patent and Trademark Office.

Colombo, L., Quevedo-Lopez, M., Chambers, J. J., Visokay, M. R., & Rotondaro, A. L. (2004). High-k gate dielectric with uniform nitrogen profile and methods for making the same. Washington, DC: U.S. Patent and Trademark Office.

Niimi, H., Khamankar, R., Chambers, J. J., Hattangady, S., & Rotondaro, A. L. (2004). Method for annealing ultra-thin, high quality gate oxide layers using oxidizer/hydrogen mixtures. Washington, DC: U.S. Patent and Trademark Office.

Rotondaro, A. L., Chambers, J. J., & Jain, A. (2004). Use of indium to define work function of p-type doped polysilicon. Washington, DC: U.S. Patent and Trademark Office.

Parsons, G. N., Chambers, J. J., & Kelly, M. J. (2003). High dielectric constant metal silicates formed by controlled metal-surface reactions. Washington, DC: U.S. Patent and Trademark Office.

Niimi, H., Chambers, J. J., Khamankar, R., & Grider, D. T. (2003). Temperature spike for uniform nitridization of ultra-thin silicon dioxide layers in transistor gates. Washington, DC: U.S. Patent and Trademark Office.

Chambers, J. J., Busch, B. W., Schulte, W. H., Gustafsson, T., Garfunkel, E., Wang, S., … Parsons, G. N. (2001). Effects of surface pretreatments on interface structure during formation of ultra-thin yttrium silicate dielectric films on silicon. APPLIED SURFACE SCIENCE, 181(1-2), 78–93. https://doi.org/10.1016/S0169-4332(01)00373-7

Chambers, J. J., & Parsons, G. N. (2001). Physical and electrical characterization of ultrathin yttrium silicate insulators on silicon. JOURNAL OF APPLIED PHYSICS, 90(2), 918–933. https://doi.org/10.1063/1.1375018

Chambers, J. J., & Parsons, G. N. (2000). Yttrium silicate formation on silicon: Effect of silicon preoxidation and nitridation on interface reaction kinetics. APPLIED PHYSICS LETTERS, 77(15), 2385–2387. https://doi.org/10.1063/1.1316073

Chambers, J. J., Min, K., & Parsons, G. N. (1998). Endpoint uniformity sensing and analysis in silicon dioxide plasma etching using in situ mass spectrometry. JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 16(6), 2996–3002. https://doi.org/10.1116/1.590332