@article{harris_priyadarshi_melamed_ortega_manohar_dooley_kriplani_davis_franzon_steer_et al._2012, title={A Transient Electrothermal Analysis of Three-Dimensional Integrated Circuits}, volume={2}, ISSN={["2156-3985"]}, DOI={10.1109/tcpmt.2011.2178414}, abstractNote={A transient electrothermal simulation of a 3-D integrated circuit (3DIC) is reported that uses dynamic modeling of the thermal network and hierarchical electrothermal simulation. This is a practical alternative to full transistor electrothermal simulations that are computationally prohibitive. Simulations are compared to measurements for a token-generating asynchronous 3DIC clocking at a maximum frequency of 1 GHz. The electrical network is based on computationally efficient electrothermal macromodels of standard and custom cells. These are linked in a physically consistent manner with a detailed thermal network extracted from an OpenAccess layout file. Coupled with model-order reduction techniques, hierarchical dynamic electrothermal simulation of large 3DICs is shown to be tractable, yielding spatial and temporal selected transistor-level thermal profiles.}, number={4}, journal={IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY}, author={Harris, T.R. and Priyadarshi, S. and Melamed, S. and Ortega, C. and Manohar, R. and Dooley, S.R. and Kriplani, N.M. and Davis, W.R. and Franzon, Paul and Steer, M.B. and et al.}, year={2012}, month={Apr}, pages={660–667} }
 @article{melamed_thorolfsson_harris_priyadarshi_franzon_steer_davis_2012, title={Junction-level thermal analysis of 3-D integrated circuits using high definition power blurring}, volume={31}, DOI={10.1109/tcad.2011.2180384}, abstractNote={The degraded thermal path of 3-D integrated circuits (3DICs) makes thermal analysis at the chip-scale an essential part of the design process. Performing an appropriate thermal analysis on such circuits requires a model with junction-level fidelity; however, the computational burden imposed by such a model is tremendous. In this paper, we present enhancements to two thermal modeling techniques for integrated circuits to make them applicable to 3DICs. First, we present a resistive mesh-based approach that improves on the fidelity of prior approaches by constructing a thermal model of the full structure of 3DICs, including the interconnect. Second, we introduce a method for dividing the thermal response caused by a heat load into a high fidelity “near response” and a lower fidelity “far response” in order to implement Power Blurring high definition (HD), a hierarchical thermal simulation approach based on Power Blurring that incorporates the resistive mesh-based models and allows for junction-level accuracy at the full-chip scale. The Power Blurring HD technique yields approximately three orders of magnitude of improvement in memory usage and up to six orders of magnitude of improvement in runtime for a three-tier synthetic aperture radar circuit, as compared to using a full-chip junction-scale resistive mesh-based model. Finally, measurement results are presented showing that Power Blurring high definition (HD) accurately determines the shape of the thermal profile of the 3DIC surface after a correction factor is added to adjust for a discrepancy in the absolute temperature values.}, number={5}, journal={IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems}, author={Melamed, S. and Thorolfsson, T. and Harris, T. R. and Priyadarshi, S. and Franzon, Paul and Steer, M. B. and Davis, W. R.}, year={2012}, pages={676–689} }