@article{lee_wu_lucovsky_2004, title={Breakdown and reliability of p-MOS devices with stacked RPECVD oxide/nitride gate dielectric under constant voltage stress}, volume={44}, ISSN={["0026-2714"]}, DOI={10.1016/j.microrel.2003.07.002}, abstractNote={In this work, the effects of voltage and temperature on the TDDB characteristics of ∼2.0 nm stacked oxide/nitride (O/N) dielectric, prepared by remote plasma enhanced CVD (RPECVD), has been investigated. The breakdown characteristics and time-to-breakdown (tBD) are recorded from p+-poly/n-Si capacitors under constant voltage stress (CVS) at different temperatures. The tBD cumulative distributions exhibit a single Weibull slope β of ∼1.9 for different applied voltages. The charge-to-breakdown (QBD) is integrated from the gate current as a function of stress times, and can be used to extract the defect generation rate. The activation energy of 0.39 eV is determined from the Arrhenius law, and the average temperature acceleration factor is about 45 between 25 and 125 °C for a constant gate voltage. The extrapolation of the TDDB lifetime with low percentile failure rate of 0.01% provides a 10-year projection for a total gate area of 0.1 cm2 on a chip at 125 °C with the Poisson area-scaling law and a constant voltage acceleration factor of ∼14.83 V−1. It is projected that the maximum safe operating voltage is ∼1.9 V for 2.07 nm O/N gate dielectric.}, number={2}, journal={MICROELECTRONICS RELIABILITY}, author={Lee, YM and Wu, YD and Lucovsky, G}, year={2004}, month={Feb}, pages={207–212} }
 @article{lee_wu_bae_hong_lucovsky_2003, title={Structural dependence of breakdown characteristics and electrical degradation in ultrathin RPECVD oxide/nitride gate dielectrics under constant voltage stress}, volume={47}, ISSN={["1879-2405"]}, DOI={10.1016/S0038-1101(02)00257-5}, abstractNote={Abstract The structural dependence of breakdown characteristics and electrical degradation in ultrathin oxide/nitride (O/N) dielectrics, prepared by remote plasma enhanced chemical vapor deposition, is investigated under constant voltage stress. In the early stage of oxide wearout, soft breakdown is a local phenomenon dominated by the tunneling current. After a given period of stress, a strong channel-length dependence of dielectric breakdown and the corresponding stress-induced leakage current from the evolution of increased tunneling current have been found. Stacked O/N dielectrics with interface nitridation demonstrate improved device performance on subthreshold swing and threshold voltage shifts after stress, indicating the suppression of stress-induced traps at the oxide/Si and oxide/drain interfaces compared to thermal oxides. Experimental evidence shows more severe breakdown and device degradation in the threshold voltage, drain current and transconductance for shorter channel PMOSFETs with O/N dielectrics. These degradations result from the enhancement of hole trapping in the gate–drain overlap region as evidenced by a positive off-state leakage current, which leads to hard breakdown, and the complete failure of device functionality.}, number={1}, journal={SOLID-STATE ELECTRONICS}, author={Lee, YM and Wu, YD and Bae, C and Hong, JG and Lucovsky, G}, year={2003}, month={Jan}, pages={71–76} }
 @article{choi_fleetwood_schrimpf_massengill_galloway_shaneyfelt_meisenheimer_dodd_schwank_lee_et al._2002, title={Long-term reliability degradation of ultrathin dielectric films due to heavy-ion irradiation}, volume={49}, ISSN={["1558-1578"]}, DOI={10.1109/TNS.2002.805389}, abstractNote={High-energy ion-irradiated 3.3-nm oxynitride film and 2.2-nm SiO/sub 2/-film MOS capacitors show premature breakdown during subsequent electrical stress. This degradation in breakdown increases with increasing ion linear energy transfer (LET), increasing ion fluence, and decreasing oxide thickness. The reliability degradation due to high-energy ion-induced latent defects is explained by a simple percolation model of conduction through SiO/sub 2/ layers with irradiation and/or electrical stress-induced defects. Monitoring the gate-leakage current reveals the presence of latent defects in the dielectric films. These results may be significant to future single-event effects and single-event gate rupture tests for MOS devices and ICs with ultrathin gate oxides.}, number={6}, journal={IEEE TRANSACTIONS ON NUCLEAR SCIENCE}, author={Choi, BK and Fleetwood, DM and Schrimpf, RD and Massengill, LW and Galloway, KF and Shaneyfelt, MR and Meisenheimer, TL and Dodd, PE and Schwank, JR and Lee, YM and et al.}, year={2002}, month={Dec}, pages={3045–3050} }
 @article{choi_fleetwood_massengill_schrimpf_galloway_shaneyfelt_meisenheimer_dodd_schwank_lee_et al._2002, title={Reliability degradation of ultra-thin oxynitride and Al2O3 gate dielectric films owing to heavy-ion irradiation}, volume={38}, DOI={10.1049/el:20020119}, abstractNote={The charge-to-breakdown of 3.3 nm oxynitride films shows significant degradation after irradiation with 342 MeV An ions. In contrast, 5.4 rim Al/sub 2/O/sub 3/ films exhibit much less degradation for similar heavy-ion stress.}, number={4}, journal={Electronics Letters}, author={Choi, B. K. and Fleetwood, D. M. and Massengill, L. W. and Schrimpf, R. D. and Galloway, K. F. and Shaneyfelt, M. R. and Meisenheimer, T. L. and Dodd, P. E. and Schwank, J. R. and Lee, Y. M. and et al.}, year={2002}, pages={157–158} }
 @article{massengill_choi_fleetwood_schrimpf_galloway_shaneyfelt_meisenheimer_dodd_schwank_lee_et al._2001, title={Heavy-ion-induced breakdown in ultra-thin gate oxides and high-k dielectrics}, volume={48}, ISSN={["1558-1578"]}, DOI={10.1109/23.983149}, abstractNote={Presents experimental results on single-event-induced breakdown in sub-5-nm plasma-enhanced SiO/sub 2/, nitrided SiO/sub 2/, Al/sub 2/O/sub 3/, HfO/sub 2/, and Zr/sub 0.4/Si/sub 1.6/O/sub 4/ dielectrics typical of current and future-generation commercial gate oxides. These advanced oxides are found to be quite resistant to ion-induced breakdown. Radiation-induced soft breakdown was observed in some films with 342 MeV Au (LET=80 MeV/mg/cm/sup 2/) but not 340 MeV I (LET=60 MeV/mg/cm/sup 2/). The critical voltage to hard breakdown was found to scale with the square root of the physical oxide thickness, not with the energy stored on the gate capacitance. Alternative dielectrics with equivalent oxide thickness substantially below their physical thickness were found to exhibit significantly higher voltage to hard breakdown than SiO/sub 2/ counterparts. All of the samples reached ion-induced hard breakdown at applied voltages well above typical operating power-supply voltages; these findings bode well for the use of advanced commercial integrated circuits in space systems.}, number={6}, journal={IEEE TRANSACTIONS ON NUCLEAR SCIENCE}, author={Massengill, LW and Choi, BK and Fleetwood, DM and Schrimpf, RD and Galloway, KF and Shaneyfelt, MR and Meisenheimer, TL and Dodd, PE and Schwank, JR and Lee, YM and et al.}, year={2001}, month={Dec}, pages={1904–1912} }
 @article{wu_lee_lucovsky_2000, title={1.6 nm oxide equivalent gate dielectrics using nitride/oxide (N/O) composites prepared by RPECVD/oxidation process}, volume={21}, ISSN={["1558-0563"]}, DOI={10.1109/55.823574}, abstractNote={Ultrathin nitride/oxide (/spl sim/1.5/0.7 nm) dual layer gate dielectrics have been formed using remote plasma enhanced CVD of nitride onto plasma-grown oxide interface layers. High accumulation capacitance (1.72 /spl mu/F/cm/sup 2/) is measured and the equivalent oxide thickness is 1.6 nm after quantum effect corrections. Compared to 1.6 nm oxides, a tunneling current reduction of more than 100 fold is found for devices with 1.6 nm N/O dielectrics due to increased film thickness and interface nitridation. Hole channel mobility decreases by about 5%, yielding very good P-MOSFET current drive. Excellent dielectric reliability and interface robustness are also demonstrated for P-MOSFET's with N/O dielectrics.}, number={3}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Wu, YD and Lee, YM and Lucovsky, G}, year={2000}, month={Mar}, pages={116–118} }
 @article{brillson_young_white_schafer_niimi_lee_lucovsky_2000, title={Depth-resolved detection and process dependence of traps at ultrathin plasma-oxidized and deposited SiO2/Si interfaces}, volume={18}, number={3}, journal={Journal of Vacuum Science & Technology. B, Microelectronics and Nanometer Structures}, author={Brillson, L. J. and Young, A. P. and White, B. D. and Schafer, J. and Niimi, H. and Lee, Y. M. and Lucovsky, G.}, year={2000}, pages={1737–1741} }
 @article{white_brillson_lee_fleetwood_schrimpf_pantelides_lee_lucovsky_2000, title={Low energy electron-excited nanoscale luminescence: A tool to detect trap activation by ionizing radiation}, volume={47}, ISSN={["1558-1578"]}, DOI={10.1109/23.903765}, abstractNote={Ultra-thin SiO/sub 2//Si gate dielectric structures exposed to heavy X-ray irradiation exhibit optical emission characteristic of interface traps. Low energy electron-excited luminescence spectroscopy with nanometer-scale depth resolution yields a characteristic spectral energy and excitation depth dependence. Ultra-thin (5 nm) oxide films on Si substrates exposed to 10 keV, 7.6 Mrad(SiO/sub 2/) [13.7 Mrad (Si)] X-ray irradiation introduces trap densities on the order of 10/sup 11/ cm/sup -2/ ev/sup -1/, localized near the intimate SiO/sub 2/-Si interface. This density is consistent with the trapped oxide and interface charge densities expected based on observed capacitance-voltages shifts of thicker oxides, their corresponding charge densities, and the proportionally smaller charge densities expected for the thinner oxide layers in this study.}, number={6}, journal={IEEE TRANSACTIONS ON NUCLEAR SCIENCE}, author={White, BD and Brillson, LJ and Lee, SC and Fleetwood, DM and Schrimpf, RD and Pantelides, ST and Lee, YM and Lucovsky, G}, year={2000}, month={Dec}, pages={2276–2280} }
 @article{wu_lucovsky_lee_2000, title={The performance and reliability of PMOSFET's with ultrathin silicon nitride/oxide stacked gate dielectrics with nitrided Si-SiO2 interfaces prepared by remote plasma enhanced CVD and post-deposition rapid thermal annealing}, volume={47}, ISSN={["1557-9646"]}, DOI={10.1109/16.848278}, abstractNote={Ultrathin (/spl sim/1.9 nm) nitride/oxide (N/O) dual layer gate dielectrics have been prepared by the remote plasma enhanced chemical vapor deposition (RPECVD) of Si/sub 3/N/sub 4/ onto oxides. Compared to PMOSFET's with heavily doped p/sup +/-poly-Si gates and oxide dielectrics, devices incorporating the RPECVD stacked nitrides display reduced tunneling current, effectively no boron penetration and improved interface characteristics. By preventing boron penetration into the bulk oxide and channel region, gate dielectric reliability and short channel effects are significantly improved. The hole mobility in devices with N/O dielectrics with equivalent oxide thickness between 1.8 nm and 3.0 nm is not significantly degraded. Because nitrogen is transported to the substrate/dielectric interface during post-deposition annealing, degradation of mobility during hot carrier stressing is significantly reduced for N/O devices. Compared with oxide, the tunneling current for N/O films with /spl sim/1.9 nm equivalent oxide thickness is lower by about an order of magnitude due to the larger physical thickness. Suppression of boron transport in nitride layers is explained by a percolation model in which boron transport is blocked in sufficiently thick nitrides, and is proportional to the oxide fraction in oxynitride alloys.}, number={7}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Wu, Y and Lucovsky, G and Lee, YM}, year={2000}, month={Jul}, pages={1361–1369} }