Works (3)

Updated: July 5th, 2023 16:02

2003 journal article

Adaptive mode control: A static-power-efficient cache design

ACM Transactions on Embedded Computing Systems, 2(3), 347–372.

By: Huiyang, M. Toburen n, E. Rotenberg n & T. Conte n

UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (OpenAlex)
Sources: NC State University Libraries, NC State University Libraries
Added: August 6, 2018

2001 conference paper

Adaptive mode control: A static-power-efficient cache design

2001 International Conference on Parallel Architectures and Compilation Techniques: Proceedings: 8-12 September, 2001, Barcelona, Catalunya, Spain, 61–70.

By: Huiyang, M. Toburen n, E. Rotenberg n & T. Conte n

TL;DR: Simulations show an average of 73% of I-cache lines and 54% of D-cache lines are put in sleep mode with an average IPC impact of only 1.7%, for 64KB caches, and this work proposes applying sleep mode only to the data store and not the tag store. (via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (OpenAlex)
Sources: NC State University Libraries, NC State University Libraries
Added: August 6, 2018

2000 journal article

System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 8(2), 129–137.

By: T. Conte n, K. Menezes*, S. Sathaye* & M. Toburen n

author keywords: high-level synthesis; instruction-level parallelism; near-optimal search; power dissipation; superscalar
TL;DR: This paper presents systematic techniques to find low-power high-performance superscalar processors tailored to specific user applications and the use of a near-optimal search to tailor a processor design to a benchmark. (via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (OpenAlex)
Source: Web Of Science
Added: August 6, 2018

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