@article{maitra_frank_narayanan_misra_cartier_2007, title={Impact of metal gates on remote phonon scattering in titanium nitride/hafnium dioxide n-channel metal-oxide-semiconductor field effect transistors-low temperature electron mobility study}, volume={102}, ISSN={["1089-7550"]}, DOI={10.1063/1.2821712}, abstractNote={We report low temperature (40–300 K) electron mobility measurements on aggressively scaled [equivalent oxide thickness (EOT)=1 nm] n-channel metal–oxide–semiconductor field effect transistors (nMOSFETs) with HfO2 gate dielectrics and metal gate electrodes (TiN). A comparison is made with conventional nMOSFETs containing HfO2 with polycrystalline Si (poly-Si) gate electrodes. No substantial change in the temperature acceleration factor is observed when poly-Si is replaced with a metal gate, showing that soft optical phonons are not significantly screened by metal gates. A qualitative argument based on an analogy between remote phonon scattering and high-resolution electron energy-loss spectroscopy (HREELS) is provided to explain the underlying physics of the observed phenomenon. It is also shown that soft optical phonon scattering is strongly damped by thin SiO2 interface layers, such that room temperature electron mobility values at EOT=1 nm become competitive with values measured in nMOSFETs with SiON gate dielectrics used in current high performance processors.}, number={11}, journal={JOURNAL OF APPLIED PHYSICS}, author={Maitra, Kingsuk and Frank, Martin M. and Narayanan, Vijay and Misra, Veena and Cartier, Eduard A.}, year={2007}, month={Dec} }
 @article{narayanan_maitra_linder_paruchuri_gusev_jamison_frank_steen_la tulipe_arnold_et al._2006, title={Process optimization for high electron mobility in nMOSFETs with aggressively scaled HfO2/metal stacks}, volume={27}, ISSN={["1558-0563"]}, DOI={10.1109/LED.2006.876312}, abstractNote={The performance of aggressively scaled (1.4nm<T/sub inv/<2.1nm) self-aligned HfO/sub 2/-based nMOSFETs with various metal gate electrodes (W, TaN, TiN, and TaSiN) is optimized. It is shown that high mobility values, competitive with oxynitride controls (SiON/poly-Si, T/sub inv//spl sim/1.8-2.1nm), can be achieved. Detailed studies of the role of interface states, remote charges in the HfO/sub 2/ layer, interfacial layer regrowth, and nitrogen-induced charge lead to the conclusion that high-temperature-induced structural modifications near the SiO/sub 2//HfO/sub 2/ interface substantially improve the electron mobility.}, number={7}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Narayanan, V. and Maitra, K. and Linder, B. P. and Paruchuri, V. K. and Gusev, E. R. and Jamison, P. and Frank, M. M. and Steen, A. L. and La Tulipe, D. and Arnold, J. and et al.}, year={2006}, month={Jul}, pages={591–594} }
 @article{maitra_bhat_2004, title={Impact of gate-to-source/drain overlap length on 80-nm CMOS circuit performance}, volume={51}, ISSN={["0018-9383"]}, DOI={10.1109/TED.2003.822347}, abstractNote={In this paper, we perform rigorous mixed-mode simulations on two-stage inverter circuit and sample-hold circuits, representative of digital, and analog applications, respectively. The impact of gate-source/drain overlap length on circuit performance in an 80-nm CMOS circuit is evaluated by varying the overlap length between 0 to 20 nm, while keeping the subthreshold leakage current constraint at 1, 10, and 100 nA//spl mu/m. Process variations about the nominal overlap length have also been accounted for. The stage delay and switch error are used as the performance metrics. The lateral peak electric field is used as the metric for the hot carrier reliability. It is demonstrated that the overlap length should be made as small as possible, in spite of the increase in series resistance, in order to get the best circuit performance and reliability.}, number={3}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Maitra, K and Bhat, N}, year={2004}, month={Mar}, pages={409–414} }
 @article{maitra_misra_2003, title={A simulation study to evaluate the feasibility of midgap workfunction metal gates in 25 nm bulk CMOS}, volume={24}, ISSN={["1558-0563"]}, DOI={10.1109/LED.2003.819267}, abstractNote={The performance of 25 nm metallurgical channel length bulk MOSFETs with midgap workfunction metal gates has been compared with conventional polysilicon gates and bandedge workfunction metal gates. Device design using pocket halo implants was implemented to achieve the required off-state leakage specification. Highly accurate, full device simulations have been performed with a linear chain of inverters taking quantum effects into consideration. Drain induced barrier lowering (DIBL) was used as an indicator of short channel effects, and the stage delay of a linear chain of inverters and the on state drive current (I/sub on/) have been identified as metrics for performance. Compared to bandedge metal gates, midgap gates suffer from lower drive currents for both NMOS and PMOS devices. On the other hand, midgap devices were comparable in their performance to N/sup +/ polysilicon gated devices and exceeded that of P/sup +/ polysilicon devices. This high performance was attributed to a lack of poly depletion in midgap metal devices and a higher degree of DIBL which resulted in a lower V/sub t/ under high drain bias providing high drive current. Conclusions have been drawn on the feasibility of using midgap metal gates to simplify process integration in future generation CMOS devices.}, number={11}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Maitra, K and Misra, V}, year={2003}, month={Nov}, pages={707–709} }