@article{varma_steer_franzon_2008, title={Improving Behavioral IO Buffer Modeling Based on IBIS}, volume={31}, ISSN={["1521-3323"]}, DOI={10.1109/tadvp.2008.2004995}, abstractNote={High level behavioral modeling is widely used in lieu of low level transistor models to ascertain the behavior of input/output (IO) drivers and receivers. The input output buffer information specification (IBIS) is one of the most widely used methodologies to model IO drivers as it satisfies the basic requirements of a behavioral model such as IP protection, simple structure, fast simulation time, and reasonable accuracy. As driver technology gets increasingly complicated and rise time of input signal gets increasingly smaller, important considerations such as simultaneous switching noise (SSN) becomes a major consideration when simulating multiple IO drivers in the integrated circuit. Unfortunately, IBIS falls short of becoming a complete IO behavioral model when simulating for SSN. This paper addresses the problem by assessing what is missing in IBIS. A method is presented for compensating for the missing information by complimenting the IBIS model with a black box that is simulator independent, without compromising with the speed that IBIS enjoys over the transistor models.}, number={4}, journal={IEEE TRANSACTIONS ON ADVANCED PACKAGING}, author={Varma, Ambrish K. and Steer, Michael and Franzon, Paul D.}, year={2008}, month={Nov}, pages={711–721} }
 @article{varma_glaser_franzon_2005, title={CAD Flows for Chip-Package CoVerification}, volume={28}, DOI={10.1109/TADVP.2004.841475}, abstractNote={A unified method is presented for layout and package design implemented within a commercial design environment that will reduce design time and enable chip-package coverification}, number={1}, journal={IEEE Transactions on Advanced Packaging}, author={Varma, A.K. and Glaser, A.W. and Franzon, Paul}, year={2005}, pages={194–202} }