@article{sarkar_ramanan_jayanti_di spigna_lee_franzon_misra_2014, title={Dual Floating Gate Unified Memory MOSFET With Simultaneous Dynamic and Non-Volatile Operation}, volume={35}, ISSN={["1558-0563"]}, DOI={10.1109/led.2013.2289751}, abstractNote={Dual floating gate flash memory has been fabricated and characterized to show dynamic operation, non-volatile operation, and simultaneous dynamic and non-volatile operation. The gate stack consists of a thin dielectric separating two floating gates sandwiched between a tunnel dielectric and interpoly dielectric. The quality of the thin dielectric that separates the floating gates is of utmost importance to retain dynamic operation. In this letter, we investigate a dual floating gate memory transistor and show its potential to combine DRAM and flash functionality in the same device.}, number={1}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Sarkar, Biplab and Ramanan, Narayanan and Jayanti, Srikant and Di Spigna, Neil and Lee, Bongmook and Franzon, Paul and Misra, Veena}, year={2014}, month={Jan}, pages={48–50} }
 @inproceedings{sarkar_jayanti_spigna_lee_misra_franzon_2013, title={Investigation of intermediate dielectric for dual floating gate MOSFET}, DOI={10.1109/nvmts.2013.6851052}, abstractNote={A dual floating gate transistor offers potential as a unified memory, with simultaneous volatile and non-volatile storage. The quality of the dielectric between the two floating gates is critical to achieving the required dynamic cycle endurance. This paper reports on the results of early experiments into the material choice and process for this dielectric.}, booktitle={2013 13th Non-Volatile Memory Technology Symposium (NVMTS)}, author={Sarkar, B. and Jayanti, S. and Spigna, N. Di and Lee, B. and Misra, V. and Franzon, Paul}, year={2013} }
 @article{chakraborti_toprakci_yang_di spigna_franzon_ghosh_2012, title={A compact dielectric elastomer tubular actuator for refreshable Braille displays}, volume={179}, ISSN={["0924-4247"]}, DOI={10.1016/j.sna.2012.02.004}, abstractNote={Electroactive polymer actuators stimulated by appropriate levels of electric field are particularly attractive for human-assist devices such as Braille. The development of a full page refreshable Braille display is very important for the integration of the visually impaired into the new era of communication. In this paper, development of a compact dielectric elastomer actuator suitable for Braille application is reported. The actuators are fabricated from commercially available silicone tubes. The tube has been rendered mechanically anisotropic through asymmetric levels of applied pretension in circumferential and axial directions in order to direct the actuation strain in the axial direction of the actuator. Key performance parameters, such as displacement, force, and response time of the actuator are investigated. The test results demonstrate the potential of the compact, lightweight, and low cost dielectric elastomer as actuators for a refreshable full page Braille display.}, journal={SENSORS AND ACTUATORS A-PHYSICAL}, author={Chakraborti, P. and Toprakci, H. A. Karahan and Yang, P. and Di Spigna, N. and Franzon, P. and Ghosh, T.}, year={2012}, month={Jun}, pages={151–157} }
 @article{schinke_di spigna_shiveshwarkar_franzon_2011, title={Computing with Novel Floating-Gate Devices}, volume={44}, ISSN={["1558-0814"]}, DOI={10.1109/mc.2010.366}, abstractNote={The authors report on the design, operation, and architectural implications of single and double floating-gate devices for nontraditional applications enabling low-power FPGAs and analog-to-digital converters, and propose a unified nonvolatile/volatile memory device.}, number={2}, journal={COMPUTER}, author={Schinke, Daniel and Di Spigna, Neil and Shiveshwarkar, Mihir and Franzon, Paul}, year={2011}, month={Feb}, pages={29–36} }
 @article{schinke_priyadarshi_pitts_di spigna_franzon_2011, title={SPICE-compatible physical model of nanocrystal floating gate devices for circuit simulation}, volume={5}, ISSN={["1751-858X"]}, DOI={10.1049/iet-cds.2010.0410}, abstractNote={The majority of nanocrystal floating gate research has been done at the device level. Circuit-level research is still in its early stages because of the lack of a physical device model appropriate for circuit simulations. In this study, a comprehensive and accurate SPICE-compatible physical equation-based model of nanocrystal floating gate devices is developed based on uniform direct tunnelling and Fowler-Nordheim tunnelling. The main contribution is a Verilog-A module that captures the physical behaviours of programming and erasing the device. A predictive NMOS model is then used for modelling the conduction channel to determine the behavioural I - V characteristics. The proposed model uses only explicit formulae resulting in fast computation appropriate for circuit simulation and can be used in any SPICE simulator supporting Verilog-A. It interacts dynamically with the rest of the circuit and includes charge leakage which enables power consumption analysis. The simulation results of the proposed model fit well to experimental results of various fabricated devices. Additionally, it is verified in HSPICE, demonstrating a significant speedup and good agreement with a numerical device simulator. This study is important in bridging the gap between device- and circuit-level research.}, number={6}, journal={IET CIRCUITS DEVICES & SYSTEMS}, author={Schinke, D. and Priyadarshi, S. and Pitts, W. Shepherd and Di Spigna, N. and Franzon, P.}, year={2011}, month={Nov}, pages={477–483} }
 @article{di spigna_chakraborti_winick_yang_ghosh_franzon_2010, title={The integration of novel EAP-based Braille cells for use in a refreshable tactile display}, volume={7642}, ISSN={["1996-756X"]}, DOI={10.1117/12.847666}, abstractNote={Structures demonstrating the viability of both the hydraulic and latching Braille dot, and the dielectric elastomer fiber Braille dot have been fabricated and characterized. A hydraulic proof-of-concept structure has achieved the necessary volumetric change required to lift a Braille dot over 0.5mm at voltages under 1000V and at speeds under 100ms. Long bimorphs have been fabricated that demonstrate large tip displacements over 2mm that could be used to mechanically latch the Braille rod in the 'up' position to achieve the force requirement. The addition of radial prestrain in dielectric elastomer tubes has reduced the wall thickness and directed the strain in the axial direction which has had a dramatic impact on their resulting characteristics. The required bias voltage for the dielectric elastomer fiber Braille dot has been reduced from 15.5kV to 8.75kV while the Braille head tip displacement of a fabricated prototype has almost tripled on average and now also exceeds the required displacement for a refreshable Braille display. Finally, potential solutions to the current shortcomings of both designs in meeting all of the requirements for such a display are discussed.}, journal={ELECTROACTIVE POLYMER ACTUATORS AND DEVICES (EAPAD) 2010}, author={Di Spigna, N. and Chakraborti, P. and Winick, D. and Yang, P. and Ghosh, T. and Franzon, P.}, year={2010} }
 @article{he_corley_lu_di spigna_he_nackashi_franzon_tour_2009, title={Controllable Molecular Modulation of Conductivity in Silicon-Based Devices}, volume={131}, ISSN={["0002-7863"]}, DOI={10.1021/ja9002537}, abstractNote={The electronic properties of silicon, such as the conductivity, are largely dependent on the density of the mobile charge carriers, which can be tuned by gating and impurity doping. When the device size scales down to the nanoscale, routine doping becomes problematic due to inhomogeneities. Here we report that a molecular monolayer, covalently grafted atop a silicon channel, can play a role similar to gating and impurity doping. Charge transfer occurs between the silicon and the molecules upon grafting, which can influence the surface band bending, and makes the molecules act as donors or acceptors. The partly charged end-groups of the grafted molecular layer may act as a top gate. The doping- and gating-like effects together lead to the observed controllable modulation of conductivity in pseudometal-oxide-semiconductor field-effect transistors (pseudo-MOSFETs). The molecular effects can even penetrate through a 4.92-mum thick silicon layer. Our results offer a paradigm for controlling electronic characteristics in nanodevices at the future diminutive technology nodes.}, number={29}, journal={JOURNAL OF THE AMERICAN CHEMICAL SOCIETY}, author={He, Tao and Corley, David A. and Lu, Meng and Di Spigna, Neil Halen and He, Jianli and Nackashi, David P. and Franzon, Paul D. and Tour, James M.}, year={2009}, month={Jul}, pages={10023–10030} }
 @article{he_lu_yao_he_chen_di spigna_nackashi_franzon_tour_2008, title={Reversible Modulation of Conductance in Silicon Devices via UV/Visible-Light Irradiation}, volume={20}, ISSN={["1521-4095"]}, DOI={10.1002/adma.200703084}, abstractNote={,}, number={23}, journal={ADVANCED MATERIALS}, author={He, Tao and Lu, Meng and Yao, Jun and He, Jianli and Chen, Bo and Di Spigna, Neil Halen and Nackashi, David P. and Franzon, Paul D. and Tour, James M.}, year={2008}, month={Dec}, pages={4541–4546} }
 @article{sonkusale_di spigna_franzon_2007, title={Uniformity analysis of wafer scale sub-25 nm wide nanowire array nanoimprint mold fabricated by PEDAL process}, volume={84}, ISSN={["0167-9317"]}, DOI={10.1016/j.mee.2007.01.210}, abstractNote={In earlier publications [S. Sonkusale, C.J. Amsinck, D.P. Nackashi, N.H. Di Spigna, D. Barlage, M. Johnson, P.D. Franzon, E. Physica, Low Dimensional Systems and Nanostructures 28 (2005) 107–114; S. Sonkusale, C.J. Amsinck, D.P. Nackashi, N.H. Di Spigna, D. Barlage, M. Johnson, P.D. Franzon, in: Proceedings of Nano Science and Technology Institute (NSTI) conference 2005, vol. 3, pp. 255.], we proposed and successfully demonstrated an unconventional lithographic technique called PEDAL process (planar edge defined alternate layer) to define wafer scale sub 25 nm nanowires and nanoimprint template. In this publication, the uniformity results on array of sixteen line-width structures with obtained by PEDAL process are presented. The average pitch of array across the 4 in. wafer was measured to be 40.8 nm with the standard deviation of 2.3 nm where as the average pitch of the lines in an array was found to be 41.5 nm with the standard deviation of 4.6 nm. After Pd lift-off the average pitch in nanowire array was measured to be 41.9 nm with standard deviation of 1.8 nm, which is close to the values obtained for the template.}, number={5-8}, journal={MICROELECTRONIC ENGINEERING}, author={Sonkusale, Sachin R. and Di Spigna, Neil H. and Franzon, Paul D.}, year={2007}, pages={1523–1527} }
 @article{di spigna_nackashi_amsinck_sonkusale_franzon_2006, title={Deterministic nanowire fanout and interconnect without any critical translational alignment}, volume={5}, ISSN={["1941-0085"]}, DOI={10.1109/TNANO.2006.876926}, abstractNote={Interfacing the nanoworld with the microworld represents a critical challenge to fully integrated nanosystems. Solutions to this problem have generally required either nanoprecision alignment or stochastic assembly. A design is presented that allows complete and deterministic fanout of regular arrays of wires from the nano- to the microworld without the need for any critical translational alignment steps. For example, deterministically connecting 10-nm wires directly to 3-mum wires would require a translational alignment to within only about 6 mum. The design also allows for nanowire interconnect and is independent of the technology used to fabricate the nanowires, enabling technologies for which alignment remains very challenging. The impact of potential fabrication errors is analyzed and a structure is fabricated that demonstrates the feasibility of such a design}, number={4}, journal={IEEE TRANSACTIONS ON NANOTECHNOLOGY}, author={Di Spigna, Neil H. and Nackashi, David P. and Amsinck, Christian J. and Sonkusale, Sachin R. and Franzon, Paul D.}, year={2006}, month={Jul}, pages={356–361} }
 @article{kriplani_nackashi_amsinck_di spigna_steer_franzon_rick_solomon_reimers_2006, title={Physically based molecular device model in a transient circuit simulator}, volume={326}, ISSN={["1873-4421"]}, DOI={10.1016/j.chemphys.2006.03.003}, abstractNote={Abstract Two efficient, physically based models for the real-time simulation of molecular device characteristics of single molecules are developed. These models assume that through-molecule tunnelling creates a steady-state Lorentzian distribution of excess electron density on the molecule and provides for smooth transitions for the electronic degrees of freedom between the tunnelling, molecular-excitation, and charge-hopping transport regimes. They are implemented in the f REEDA™ transient circuit simulator to allow for the full integration of nanoscopic molecular devices in standard packages that simulate entire devices including CMOS circuitry. Methods are presented to estimate the parameters used in the models via either direct experimental measurement or density-functional calculations. The models require 6–8 orders of magnitude less computer time than do full a priori simulations of the properties of molecular components. Consequently, molecular components can be efficiently implemented in circuit simulators. The molecular-component models are tested by comparison with experimental results reported for 1,4-benzenedithiol.}, number={1}, journal={CHEMICAL PHYSICS}, author={Kriplani, Nikhil M. and Nackashi, David P. and Amsinck, Christian J. and Di Spigna, Neil H. and Steer, Michael B. and Franzon, Paul D. and Rick, Ramon L. and Solomon, Gemma C. and Reimers, Jeffrey R.}, year={2006}, month={Jul}, pages={188–196} }
 @article{sonkusale_amsinck_nackashi_di spigna_barlage_johnson_franzon_2005, title={Fabrication of wafer scale, aligned sub-25 nm nanowire and nanowire templates using planar edge defined alternate layer process}, volume={28}, ISSN={["1873-1759"]}, DOI={10.1016/j.physe.2005.01.010}, abstractNote={We have demonstrated a new planar edge defined alternate layer (PEDAL) process to make sub-25 nm nanowires across the whole wafer. The PEDAL process is useful in the fabrication of metal nanowires directly onto the wafer by shadow metallization and has the ability to fabricate sub-10 nm nanowires with 20 nm pitch. The process can also be used to make templates for the nano-imprinting with which the crossbar structures can be fabricated. The process involves defining the edge by etching a trench patterned by conventional i-line lithography, followed by deposition of alternating layers of silicon nitride and crystallized a-Si. The thickness of these layers determines the width and spacing of the nanowires. Later the stack is planarized to the edge of the trench by spinning polymer Shipley 1813 and then dry etching the polymer, nitride and polysilicon stack with non-selective RIE etch recipe. Selective wet etch of either nitride or polysilicon gives us the array of an aligned nanowires template. After shadow metallization of the required metal, we get metal nanowires on the wafer. The process has the flexibility of routing the nanowires around the logic and memory modules all across the wafer. The fabrication facilities required for the process are readily available and this process provides the great alternative to existing slow and/or costly nanowire patterning techniques.}, number={2}, journal={PHYSICA E-LOW-DIMENSIONAL SYSTEMS & NANOSTRUCTURES}, author={Sonkusale, SR and Amsinck, CJ and Nackashi, DP and Di Spigna, NH and Barlage, D and Johnson, M and Franzon, PD}, year={2005}, month={Jul}, pages={107–114} }