@article{park_ozbek_ma_veety_morgensen_barlage_wheeler_johnson_2010, title={An analytical model of source injection for N-type enhancement mode GaN-based Schottky Source/Drain MOSFET's with experimental demonstration}, volume={54}, ISSN={["0038-1101"]}, DOI={10.1016/j.sse.2010.06.013}, abstractNote={Abstract This study investigates the effect of the Gate-to-Source/Drain overlap structure of a GaN Schottky Source/Drain MOSFET. The Gate-to-Source overlap structure of the device allows the gate electric field to reduce the height of the Nickel(source)–GaN Schottky barrier near the SiO 2 –GaN interface at the source side, injecting more thermionically generated carriers over the partially reduced Schottky barrier. Based on this Schottky barrier lowering mechanism, an analytical model was developed. The analytical model shows that the reduction of the Schottky barrier height by 0.25 eV increases the on-state drain current by two orders of magnitude, which is in agreement of the previously reported TCAD simulation result in [6] . A specifically designed GaN Schottky Source/Drain MOSFET with the Gate-to-Source/Drain overlap structure was fabricated and characterized; the I D – V DS characteristic of the device shows that the on-state drain current of the device was increased by up to 160× compared to the same kind of device without the overlap structure (reported in Lei Ma (2007) [7] ), which is in agreement with the analytical model described herein.}, number={12}, journal={SOLID-STATE ELECTRONICS}, author={Park, Jaehoon and Ozbek, Ayse M. and Ma, Lei and Veety, Matthew T. and Morgensen, Michael P. and Barlage, Douglas W. and Wheeler, Virginia D. and Johnson, Mark A. L.}, year={2010}, month={Dec}, pages={1680–1685} }
 @misc{jin_zeng_ma_barlage_2007, title={Analytical threshold voltage model with TCAD simulation verification for design and evaluation of tri-gate MOSFETs}, volume={51}, ISSN={["0038-1101"]}, DOI={10.1016/j.sse.2007.01.023}, abstractNote={Abstract The dynamics of the threshold voltage calculation is evaluated for the tri-gate architecture of device. The 3-D poisson’s equation with eight boundary conditions is solved analytically and an analytical threshold model for tri-gate Si MOSFET device is developed. TCAD simulation result of the same device structure is also presented and it agrees well with our threshold analytical model. Furthermore, this analytical threshold model is capable of doing rudimentary first order comparisons of the threshold voltage with respect to device dimensions and semiconductor material type.}, number={3}, journal={SOLID-STATE ELECTRONICS}, author={Jin, Yawei and Zeng, Chang and Ma, Lei and Barlage, Doug}, year={2007}, month={Mar}, pages={347–353} }