@article{kim_han_osburn_2004, title={Effect of post-metallization annealing for alternative gate stack devices}, volume={151}, ISSN={["1945-7111"]}, DOI={10.1149/1.1636181}, abstractNote={The effect of the post-metallization annealing of devices having HfO 2 , La 2 O 3 , or Y 2 O 3 dielectrics and poly-Si or TaN gate electrodes was studied. Forming gas (10% H 2 /90% N 2 ) annealing at 400°C enhanced drive current and channel mobility of devices having 1.2 nm HfO 2 gate dielectrics, by eliminating interface states. Post-metal annealing in 10% D 2 for 1.2 nm HfO 2 gate dielectrics resulted in larger enhancements in drive current and device channel mobility than forming gas annealing. Similar enhancements of the device characteristics were observed in La 2 O 3 (300 mV shift in both flatband and threshold voltage) and Y 2 O 3 (200 mV shift only in threshold voltage) materials. Annealing in pure nitrogen was found to degrade the dielectric quality of HfO 2 , including a decrease in device current and 50% lower capacitance.}, number={2}, journal={JOURNAL OF THE ELECTROCHEMICAL SOCIETY}, author={Kim, I and Han, SK and Osburn, CM}, year={2004}, month={Feb}, pages={F29–F35} }
 @article{kim_han_osburn_2004, title={Stability of advanced gate stack devices}, volume={151}, ISSN={["1945-7111"]}, DOI={10.1149/1.1636180}, abstractNote={The stability of poly-Si gated HfO 2 (∼1.2 nm equivalent oxide thickness, EOT) and Y 2 O 3 (∼3.1 nm EOT) n-channel metal oxide semiconductor field effect transistor devices were assessed after constant current stressing of the gate. The changes in threshold voltage and transconductance were measured as a function of stress time and stress current over the range of 10 -3 to 10 5 C of injected charge per square centimeter. With forming gas annealed HfO 2 , positive shifts in the threshold voltage exhibited a power-law dependence. Under high stressing conditions, a power-law dependence of degradation of threshold voltage on the injected charge (∼Q 0.1 ) was observed. Stressing at high current was seen to generate traps. Stressing at low current revealed a saturation of the threshold voltage after modest stressing times. Stressing on deuterium annealed sample showed less V t and g m shift (under high injection conditions), which is attributed to the effectiveness of heavier D 2 in preventing trap generation under high stressing conditions. With Y 2 O 3 , stressed at similar electric fields, the threshold voltage shifted negatively and the transconductance increased.}, number={2}, journal={JOURNAL OF THE ELECTROCHEMICAL SOCIETY}, author={Kim, I and Han, SK and Osburn, CM}, year={2004}, month={Feb}, pages={F22–F28} }
 @article{osburn_kim_han_de_yee_gannavaram_lee_lee_luo_zhu_et al._2002, title={Vertically scaled MOSFET gate stacks and junctions: How far are we likely to go?}, volume={46}, ISSN={["2151-8556"]}, DOI={10.1147/rd.462.0299}, abstractNote={The vertical scaling requirements for gate stacks and for shallow extension junctions are reviewed. For gate stacks, considerable progress has been made in optimizing oxide/nitride and oxynitride dielectrics to reduce boron penetration and dielectric leakage compared to pure SiO2 in order to allow sub-2-nm dielectrics. Several promising alternative material candidates exist for 1-nm equivalent oxide thickness (EOT)-for example, HfO2, ZrO2, and their silicates. Nevertheless, considerable challenges lie ahead if we are to achieve an EOT of less than 0.5 nm. If only a single molecular interface layer of oxide is needed to preserve high channel mobility, it seems likely that an EOT of 0.4-0.5 nm would represent the physical limit of dielectric scaling, but even then with a very high leakage (∼105 A/cm2). For junctions, the main challenge lies in providing low parasitic series resistance as depths are scaled in order to reduce short-channel effects. Because contacts are ultimately expected to dominate the parasitic resistance, low-barrier-height contacts and/or very heavily doped junctions will be required. While ion implantation and annealing processes can certainly be extended to meet the junction-depth and series-resistance requirements for additional generations, alternative low-temperature deposition processes that produce either metastably or extraordinarily activated, abruptly doped regions seem better suited to solve the contact resistance problem.}, number={2-3}, journal={IBM JOURNAL OF RESEARCH AND DEVELOPMENT}, author={Osburn, CM and Kim, I and Han, SK and De, I and Yee, KF and Gannavaram, S and Lee, SJ and Lee, CH and Luo, ZJ and Zhu, W and et al.}, year={2002}, pages={299–315} }
 @article{han_mcclure_wolden_vlahovic_soldi_sitar_2000, title={Fabrication and testing of a microstrip particle detector based on highly oriented diamond films}, volume={9}, number={3-6}, journal={Diamond and Related Materials}, author={Han, S. K. and McClure, M. T. and Wolden, C. A. and Vlahovic, B. and Soldi, A. and Sitar, S.}, year={2000}, pages={1008–1012} }
 @article{wolden_han_mcclure_sitar_prater_1997, title={Highly oriented diamond deposited using a low pressure flat flame}, volume={32}, ISSN={["0167-577X"]}, DOI={10.1016/S0167-577X(97)00003-7}, abstractNote={A multi-step process for the achievement of highly oriented, 〈100〉 textured diamond films on silicon using flat flame deposition has been developed. First, a bias-enhanced technique was used to achieve oriented nuclei on a Si 〈100〉 substrate in a microwave plasma reactor. Substrates were then transferred to the combustion system and rapidly grown into coalesced 〈100〉 films at a growth rate of 4–5 μm/h. X-ray texture analysis was used to characterize the films. It showed a 12 ° misalignment of the crystallites with respect to the surface normal, while the azimuthal misalignment was measured to be 20 °.}, number={1}, journal={MATERIALS LETTERS}, author={Wolden, CA and Han, SK and McClure, MT and Sitar, Z and Prater, JT}, year={1997}, month={Jul}, pages={9–12} }