@article{shekhar_ramaprasad_sarkar_mueller_2015, title={Architecture aware semi partitioned real-time scheduling on multicore platforms}, volume={51}, ISSN={["1573-1383"]}, DOI={10.1007/s11241-015-9221-4}, number={3}, journal={REAL-TIME SYSTEMS}, author={Shekhar, Mayank and Ramaprasad, Harini and Sarkar, Abhik and Mueller, Frank}, year={2015}, month={Jun}, pages={274–313} }
 @article{sarkar_mueller_ramaprasad_2015, title={Static Task Partitioning for Locked Caches in Multicore Real-Time Systems}, volume={14}, ISSN={["1558-3465"]}, DOI={10.1145/2638557}, abstractNote={
            Growing processing demand on multitasking real-time systems can be met by employing scalable multicore architectures. For such environments, locking cache lines for hard real-time systems ensures timing predictability of data references and may lower worst-case execution time. This work studies the benefits of cache locking on massive multicore architectures with private caches in the context of hard real-time systems. In shared cache architectures, the cache is a single resource shared among
            all
            of the tasks. However, in scalable cache architectures with private caches, conflicts exist only among the tasks scheduled on one core. This calls for a cache-aware allocation of tasks onto cores.
          }, number={1}, journal={ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS}, author={Sarkar, Abhik and Mueller, Frank and Ramaprasad, Harini}, year={2015}, month={Jan} }
 @article{sarkar_chakravartty_2013, title={Prediction of flow stress in cadmium using constitutive equation and artificial neural network approach}, volume={22}, number={10}, journal={Journal of Materials Engineering and Performance}, author={Sarkar, A. and Chakravartty, J. K.}, year={2013}, pages={2982–2989} }
 @inproceedings{sarkar_mueller_ramaprasad_2012, title={Static task partitioning for locked caches in multi-core real-time systems}, DOI={10.1145/2380403.2380434}, abstractNote={Locking cache lines in hard real-time systems is a common means to ensure timing predictability of data references and to lower bounds on worst-case execution time, especially in a multi-tasking environment. Growing processing demand on multi-tasking real-time systems can be met by employing scalable multi-core architectures, like the recently introduced tile-based architectures. This paper studies the use of cache locking on massive multi-core architectures with private caches in the context of hard real-time systems. In shared cache architectures, a single resource is shared among {\em all} the tasks. However, in scalable cache architectures with private caches, conflicts exist only among the tasks scheduled on one core. This calls for a cache-aware allocation of tasks onto cores. Our work extends the cache-unaware First Fit Decreasing (FFD) algorithm with a Naive locked First Fit Decreasing (NFFD) policy. We further propose two cache-aware static scheduling schemes: (1) Greedy First Fit Decreasing (GFFD) and (2) Colored First Fit Decreasing (CoFFD). This work contributes an adaptation of these algorithms for conflict resolution of partially locked regions. Experiments indicate that NFFD is capable of scheduling high utilization task sets that FFD cannot schedule. Experiments also show that CoFFD consistently outperforms GFFD resulting in lower number of cores and lower system utilization. CoFFD reduces the number of core requirements from 30% to 60% compared to NFFD. With partial locking, the number of cores in some cases is reduced by almost 50% with an increase in system utilization of 10%. Overall, this work is unique in considering the challenges of future multi-core architectures for real-time systems and provides key insights into task partitioning with locked caches for architectures with private caches.}, booktitle={Cases'12: proceedings of the 2012 ACM International Conference on Compilers, Architectures and Synthesis for Embedded Systems}, author={Sarkar, A. and Mueller, F. and Ramaprasad, H.}, year={2012}, pages={161–170} }
 @article{sarkar_mueller_ramaprasad_2011, title={Predictable Task Migration for Locked Caches in Multi-Core Systems}, volume={46}, ISSN={["1558-1160"]}, DOI={10.1145/2016603.1967696}, abstractNote={Locking cache lines in hard real-time systems is a common means of achieving predictability of cache access behavior and tightening as well as reducing worst case execution time, especially in a multitasking environment. However, cache locking poses a challenge for multi-core hard real-time systems since theoretically optimal scheduling techniques on multi-core architectures assume zero cost for task migration. Tasks with locked cache lines need to proactively migrate these lines before the next invocation of the task. Otherwise, cache locking on multi-core architectures becomes useless as predictability is compromised.}, number={5}, journal={ACM SIGPLAN NOTICES}, author={Sarkar, Abhik and Mueller, Frank and Ramaprasad, Harini}, year={2011}, month={May}, pages={131–140} }
 @inproceedings{sarkar_mueller_ramaprasad_2011, title={Predictable task migration for locked caches in multi-core systems}, DOI={10.1145/1967677.1967696}, abstractNote={Locking cache lines in hard real-time systems is a common means of achieving predictability of cache access behavior and tightening as well as reducing worst case execution time, especially in a multitasking environment. However, cache locking poses a challenge for multi-core hard real-time systems since theoretically optimal scheduling techniques on multi-core architectures assume zero cost for task migration. Tasks with locked cache lines need to proactively migrate these lines before the next invocation of the task. Otherwise, cache locking on multi-core architectures becomes useless as predictability is compromised.
 This paper proposes hardware-based push-assisted cache migration as a means to retain locks on cache lines across migrations. We extend the push-assisted migration model with several cache migration techniques to efficiently retain locked cache lines on a bus-based chip multi-processor architecture. We also provide deterministic migration delay bounds that help the scheduler decide which migration technique(s) to utilize to relocate a single or multiple tasks. This information also allows the scheduler to determine feasibility of task migrations, which is critical for the safety of any hard real-time system. Such proactive migration of locked cache lines in multi-cores is unprecedented to our knowledge.}, booktitle={LCTES 11: Proceedings of the ACM Sigplan/Sigbed 2011 Conference on Languages, Complilers, Tools and Theory for Embedded Systems}, author={Sarkar, A. and Mueller, F. and Ramaprasad, H.}, year={2011}, pages={131–140} }
 @inproceedings{sarkar_alsabbagh_murty, title={Effect of low dose neutron irradiation on tensile behavior of ht-9 steel at room temperature}, booktitle={TMS 2014 Supplemental Proceedings}, author={Sarkar, A. and Alsabbagh, A. H. and Murty, K. L.}, pages={147–154} }