@article{moorthy_aberg_olimmah_yang_rahman_lemmon_yu_husain_2020, title={Estimation, Minimization, and Validation of Commutation Loop Inductance for a 135-kW SiC EV Traction Inverter}, volume={8}, ISSN={["2168-6785"]}, DOI={10.1109/JESTPE.2019.2952884}, abstractNote={With growing interests in low-inductance silicon carbide (SiC)-based power module packaging, it is vital to focus on system-level design aspects to facilitate easy integration of the modules and reap system-level benefits. To effectively utilize the low-inductance modules, busbar and interconnects should also be designed with low stray inductances. A holistic investigation of the flux path and flux cancellations in the module-busbar assembly, which can be treated as differentially coupled series inductors, is thus mandatory for a system-level design. This article presents a busbar design, which can be adopted to effectively integrate the CREE’s low-inductance 1.2-/1.7-kV SiC power modules. This article also proposes a novel measurement technique to measure the inductance of the module-busbar assembly as a whole rather than deducing it from individual components. The inductance of the overall commutation loop of the inverter that encompasses the SiC power module, interconnects, and printed circuit board (PCB) busbar has been estimated using finite-element analysis (FEA). Insights gained from FEA provided the guidelines to decide the placement of the decoupling capacitors in the busbar to minimize the overall commutation loop inductance from 12.8 to 7.4 nH, which resulted in a significant reduction in the device voltage overshoot. The simulation results have been validated through measurements using an impedance analyzer (ZA) with less than 5% difference between the extracted loop inductance from FEA and measurements. The busbar design study and the measurement technique discussed in this article can be easily extended to other power module packages. Finally, the 135-kW inverter has been compared to a similar high-power inverter utilizing a laminated busbar to highlight the performance of the former.}, number={1}, journal={IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS}, author={Moorthy, Radha Sree Krishna and Aberg, Bryce and Olimmah, Marshal and Yang, Li and Rahman, Dhrubo and Lemmon, Andrew N. and Yu, Wensong and Husain, Iqbal}, year={2020}, month={Mar}, pages={286–297} }
 @inproceedings{aberg_moorthy_yang_yu_husain_2018, title={Estimation and minimization of power loop inductance in 135 kW SiC traction inverter}, DOI={10.1109/apec.2018.8341257}, abstractNote={The paper discusses the estimation and minimization of commutation loop inductance for a printed circuit board (PCB) busbar based 135 kW SiC inverter with a 1 kV DC link using finite element analysis (FEA) simulations. For the inductance estimation of the power module (Wolfspeed: HT-3231-R), PCB busbar, and customized interconnects constituting the commutation loop have been modelled accurately in Ansys Q3D Extractor. Based on the simulation results, subsequent modification to the original PCB busbar design has been proposed to lower the loop inductance. FEA simulation results have resulted in an optimized PCB busbar with lower commutation loop inductance, thereby limiting the device voltage spike well below its rated value. Loop inductance results from the Q3D simulation have been validated through double pulse tests (DPT) and the performance improvements achieved therefore have been highlighted.}, booktitle={Thirty-third annual ieee applied power electronics conference and exposition (apec 2018)}, author={Aberg, B. and Moorthy, R. S. K. and Yang, L. and Yu, Wensong and Husain, I.}, year={2018}, pages={1772–1777} }