@inproceedings{lee_huang_huang_brunt_2013, title={An analytical investigation of the effect of varied buffer layer designs on the turn-off speed for 4H-SiC IGBTs}, DOI={10.1109/wipda.2013.6695559}, abstractNote={We propose a criterion to quantify the relationship between buffer layer parameters at a given total charge and turn-off speed for 4H-SiC IGBTs. Three phases of voltage ramp are analytically discussed during the inductive load turn-off by solving each corresponding continuity equation. Extra emphasis will be placed on Phase II - a transition phase in between the initial voltage ramp and punch-through.}, booktitle={2013 1st IEEE Workshop on Wide Bandgap Power Devices and Applications (WiPDA)}, author={Lee, M. C. and Huang, X. and Huang, A. and Brunt, E.}, year={2013}, pages={44–47} }
 @article{sung_van brunt_baliga_huang_2012, title={A Comparative Study of Gate Structures for 9.4-kV4H-SiC Normally On Vertical JFETs}, volume={59}, ISSN={["0018-9383"]}, DOI={10.1109/ted.2012.2203337}, abstractNote={This paper reports the development of 9.4-kV 4H-SiC normally on lateral-channel vertical JFETs. The developed JFETs utilize a buried layer to create a lateral conduction channel, shielding the source from the effects of drain bias. The lowest measured <formula formulatype="inline"><tex Notation="TeX">$R_{\rm on, sp}$</tex></formula> was 127 <formula formulatype="inline"><tex Notation="TeX">$\hbox{m}\Omega\cdot\hbox{cm}^{2}$</tex></formula>. Measurements indicate that the channel resistivity can be further reduced by channel optimization. The fabricated JFETs exhibit pentode-like <formula formulatype="inline"><tex Notation="TeX">$I_{D}$</tex></formula>–<formula formulatype="inline"><tex Notation="TeX">$V_{\rm DS}$ </tex></formula> characteristics with a high forward direct-current blocking gain of over 500. This paper provides a comparative study of gate structures in order to achieve the lowest on -state switching losses and to provide stable forward blocking characteristics for a normally on JFET.}, number={9}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Sung, Woongje and Van Brunt, Edward and Baliga, B. Jayant and Huang, Alex Q.}, year={2012}, month={Sep}, pages={2417–2423} }
 @inproceedings{van brunt_huang_butschen_de doncker_2012, title={Dual-GCT design criteria and voltage scaling}, DOI={10.1109/ecce.2012.6342394}, abstractNote={Global optimization has been performed to derive optimal Dual-GCT structures for 3.3 kV, 5 kV, and 6.5 kV class devices by using numerical simulation results. A treatment of all relevant physical concepts for both standard- and Dual-GCTs are taken into account in the optimization process, providing an insight into the effect of design parameters such as minority carrier lifetime, buffer region design, and device geometry. The results indicate that within the scope of a Dual Active Bridge power converter application, the Dual-GCT can provide more than 54 % improvement in the current density when compared to equivalent conventional devices for each of the device ratings examined, which verifies the scalability of the Dual-GCT concept.}, booktitle={2012 IEEE Energy Conversion Congress and Exposition (ECCE)}, author={Van Brunt, E. and Huang, A. Q. and Butschen, T. and De Doncker, R. W.}, year={2012}, pages={2596–2603} }
 @article{huang_van brunt_baliga_huang_2012, title={Orthogonal Positive-Bevel Termination for Chip-Size SiC Reverse Blocking Devices}, volume={33}, ISSN={["1558-0563"]}, DOI={10.1109/led.2012.2215003}, abstractNote={Symmetric blocking power semiconductor switches require positive-bevel edge terminations for the reverse blocking p-n junction. This technique has been extensively applied to silicon wafer-size devices with high current ratings. In this letter, we propose and experimentally demonstrate, for the first time, that an orthogonal positive-bevel termination can be used for the reverse blocking junction of chip-size SiC devices. The edge termination was formed by sawing the SiC wafer with a V-shaped dicing blade. For proof of concept, our experiment was done on a SiC wafer with a 15.8-μm 6.1 × 1015 cm-3 p-type epitaxial layer grown on an N+ substrate. The positive-bevel termination resulted in a breakdown voltage of over 1000 V as limited by reach-through breakdown even without removal of damage from the sawing. The leakage current was found to be reduced by two orders of magnitude after reactive ion etching of the SiC bevel surface to remove the sawing damage.}, number={11}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Huang, Xing and Van Brunt, Edward and Baliga, B. Jayant and Huang, Alex Q.}, year={2012}, month={Nov}, pages={1592–1594} }