@article{charles_franzon_2015, title={A Multitier Study on Various Stacking Topologies of TSV-Based PDN Systems Using On-Chip Decoupling Capacitor Models}, volume={5}, ISSN={["2156-3985"]}, DOI={10.1109/tcpmt.2015.2416196}, abstractNote={We studied the impedance characteristics of through-silicon via (TSV)-based power delivery networks (PDNs) for hierarchical on-die simulation and interconnect noise analysis. This paper compares the quality of power delivery in 3-D stacking scenarios for three distinct chip stacking topologies: 1) face-to-back (F2B); 2) face-to-face (F2F); and 3) back-to-back (B2B). Quantitatively, this paper compared the impedance noise level between the three stacking topologies and found the PDN impedance noise of F2F chip stacking to be relatively lower than F2B and B2B chip stacking topologies. A power delivery impedance below 1 Ω for F2F chip stacking topology was possible up to 2 GHz. However, for F2B and B2B chip stacking, the PDN impedance could not get beyond sub-1 Ω. The impedance was simulated between 0.1 and 20 GHz. Among power grid and power and ground TSV models presented in this paper, we also present and implemented a metal-insulator-metal capacitor model written as a complex impedance equation. With capacitor dimensions similar to the unit cell gird size (200 μm × 200 μm), the capacitance density (per unit area) ranged from 0.062 pF/μm2 to 5.325 fF/μm2.}, number={4}, journal={IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY}, author={Charles, Gary and Franzon, Paul D.}, year={2015}, month={Apr}, pages={541–550} }
 @inproceedings{charles_franzon_2012, title={Comparison of TSV-based PDN-design effects using various stacking topology methods}, DOI={10.1109/epeps.2012.6457848}, abstractNote={In this study, we estimate, compare and analyze the PDN effects of four chip-stacking topologies. The chip-stacking topologies are: (1) F2B; (2) F2F; (3) B2F; and (4) B2B. The arrangement of various on-chip interconnect elements based on the chip-stacking topologies specific to the design of 3D IC-PDN, varies in impedance properties. To reduce the impedance effects NMOS decap unit cells are integrated into PDN system to suppress 3D-SSN. Conclusively, the results of the case study indicate B2F and F2B die stacking topologies results in lower impedance effects relative to F2F topology.}, booktitle={Ieee conference on electrical performance of electronic packaging and}, author={Charles, G. and Franzon, Paul}, year={2012}, pages={83–86} }
 @inproceedings{charles_franzon_kim_levin_2011, title={Analysis and approach of TSV-based hierarchical power distribution networks for estimating 1st-droop and resonant noise in 3DIC}, DOI={10.1109/epeps.2011.6100243}, abstractNote={In this paper, we model and analyse a hierarchical TSV-based chip-package co-design of the power delivery network (PDN) for three-dimensional integrated circuits (3DICs). It is a significant design consideration to combine chip/package PDN structures, accurately characterize and quantify their overall impedance, 1st-droop effect and resonant noise behaviour for multi-stacked chips. To better understand how to reduce noise, particularly simultaneous switching noise (SSN) and determine voltage drop impact on power delivery networks for 3DICs, an analytical model is enhanced and applied to estimate the different noise levels of hierarchical TSV-based PDN structures. The on-chip parasitic capacitances and intentionally added decoupling capacitors help counter any Ldi/dt variations from the power supply rails as a result of the inductive effects in TSVs. With technology interest in embedded applications, the hierarchical chip-package TSV-based PDN design is modeled after a multi-stacked memory subsystem, a silicon interposer and package structure. A segmentation-based method is used to calculate the overall impedance of the hierarchical PDN system. An analytical expression is modified and used to quantify the transient response characteristics of 1st-droop and resonant noise property.}, booktitle={Ieee conference on electrical performance of electronic packaging and}, author={Charles, G. and Franzon, Paul and Kim, J. and Levin, A.}, year={2011}, pages={267–270} }