Works (4)
Updated: March 29th, 2024 05:02
2023 article
A Spatio-Temporal Switchable Data Prefetcher for Convolutional Neural Networks
2023 20TH INTERNATIONAL SOC DESIGN CONFERENCE, ISOCC, pp. 141–142.
author keywords: Data prefetching; spatio-temporal prefetcher; convolutional neural neworks
TL;DR:
A spatio-temporal switchable data prefetcher that can adapt to the locality characteristics of CNN models and improves system performance by 33.8% over a baseline with no data prefetcher and 21% over the best-performing prior spatio-temporal prefetcher.
(via Semantic Scholar)
Source: Web Of Science
Added: March 25, 2024
2023 article
CryptoMMU: Enabling Scalable and Secure Access Control of Third-Party Accelerators
56TH IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, MICRO 2023, pp. 32–48.
author keywords: IOMMU; accelerator-rich architecture; access control; cryptography
TL;DR:
This paper proposes a novel scheme, CryptoMMU, to delegate the translation processes to accelerators, whereas the authentication of the targeted address is elegantly performed using a cryptography-based approach, providing better scalability.
(via Semantic Scholar)
dl.acm.org (publisher PDF)
Source: Web Of Science
Added: March 25, 2024
2023 article
ERAS: A Flexible and Scalable Framework for Seamless Integration of RTL Models with Structural Simulation Toolkit
2023 IEEE INTERNATIONAL SYMPOSIUM ON WORKLOAD CHARACTERIZATION, IISWC, pp. 196–200.
author keywords: RTL; architectural simulator; SST; gem5
TL;DR:
This work proposes a framework, ERAS, that enables seamless integration of RTL IP models with high-level architectural simulators, such as Structural Simulation Toolkit (SST), and leverages SST’s multi-thread support to enhance simulation speed, effectively overcoming a key bottleneck of detailed RTL simulation.
(via Semantic Scholar)
Source: Web Of Science
Added: January 2, 2024
2023 article
SDM: Sharing-enabled Disaggregated Memory System with Cache Coherent Compute Express Link
2023 32ND INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES, PACT, pp. 86–98.
author keywords: Disaggregated memory; CXL; cache coherency
TL;DR:
SDM is proposed, a sharing-enabled, cache-coherent disaggregated memory system that effectively utilizes modern interconnect technology that outperforms the optimized baseline system, and introduces resource management and speculative memory access mechanisms that do not interfere with normal memory transaction channels.
(via Semantic Scholar)
Source: Web Of Science
Added: March 25, 2024
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