Kijeong Han

1.2-kV 4H-SiC SenseFET With Monolithically Integrated Sensing Resistor

IEEE ELECTRON DEVICE LETTERS, 41(3), 437–440.

2.3 kV 4H-SiC Accumulation-Channel Split-Gate Planar Power MOSFETs With Reduced Gate Charge

IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 8(1), 499–504.

600 V 4H-SiC MOSFETs Fabricated in Commercial Foundry With Reduced Gate Oxide Thickness of 27 nm to Achieve IGBT-Compatible Gate Drive of 15 V (vol 40, pg 1792, 2019)

Agarwal, A., Han, K., & Jayant Baliga, B. (2020, January). IEEE ELECTRON DEVICE LETTERS, Vol. 41, pp. 195–195.

Comparison of 2.3-kV 4H-SiC Accumulation-Channel Planar Power MOSFETs Fabricated With Linear, Square, Hexagonal, and Octagonal Cell Topologies

IEEE TRANSACTIONS ON ELECTRON DEVICES, 67(9), 3673–3678.

600 V 4H-SiC MOSFETs Fabricated in Commercial Foundry With Reduced Gate Oxide Thickness of 27 nm to Achieve IGBT-Compatible Gate Drive of 15 V

IEEE ELECTRON DEVICE LETTERS, 40(11), 1792–1795.

Analysis and Experimental Quantification of 1.2-kV 4H-SiC Split-Gate Octagonal MOSFET

IEEE ELECTRON DEVICE LETTERS, 40(7), 1163–1166.

Comparison of Four Cell Topologies for 1.2-kV Accumulation- and Inversion-Channel 4H-SiC MOSFETs: Analysis and Experimental Results

IEEE TRANSACTIONS ON ELECTRON DEVICES, 66(5), 2321–2326.

Comprehensive Physics of Third Quadrant Characteristics for Accumulation- and Inversion-Channel 1.2-kV 4H-SiC MOSFETs

IEEE TRANSACTIONS ON ELECTRON DEVICES, 66(9), 3923–3928.

Impact of Cell Topology on Characteristics of 600V 4H-SiC Planar MOSFETs

IEEE ELECTRON DEVICE LETTERS, 40(5), 773–776.

The 1.2-kV 4H-SiC OCTFET: A New Cell Topology With Improved High-Frequency Figures-of-Merit

IEEE ELECTRON DEVICE LETTERS, 40(2), 299–302.

A novel 1.2 kV 4H-SiC buffered-gate (BG) MOSFET: Analysis and experimental results

IEEE Electron Device Letters, 39(2), 248–251.

Applications and characterization of four quadrant GaN switch

2017 ieee energy conversion congress and exposition (ecce), 1967–1974.

Split-gate 1.2-kV 4H-SiC MOSFET: Analysis and experimental validation

IEEE Electron Device Letters, 38(10), 1437–1440.

Optimization of the JFET region of 1.2kV SiC MOSFETs for improved high frequency figure of merit (HF-FOM)

Sung, W. J., Han, K. J., & Baliga, B. J. 2017 IEEE 5th Workshop on Wide Bandgap Power Devices and Applications (WIPDA), 238–241.