@article{bhattacharya_narwal_shah_baliga_agarwal_kanale_han_hopkins_cheng_2023, title={Power Conversion Systems Enabled by SiC BiDFET Device}, volume={10}, ISSN={["2329-9215"]}, url={https://doi.org/10.1109/MPEL.2023.3237060}, DOI={10.1109/MPEL.2023.3237060}, abstractNote={The BiDirectional Field-Effect Transistor (BiDFET) can enable circuit topologies requiring four-quadrant switches, that were earlier designed using discrete combinations of MOSFETs, IGBTs, GaN HEMTs, and PiN diodes. The monolithic nature of the BiDFET allows lower device count, smaller switch volume, lower inductance, and simpler packaging, and hence more reliable and commercially viable implementation in power electronics converters. The matrix converter topologies, now feasible using BiDFETs, can eliminate the bulky and unreliable dc link capacitors or inductors required for conventional voltage-source or current-source converters in ac–ac and ac–dc applications. The 1.2 kV BiDFET has the potential to disrupt all the applications utilizing 1.2 kV switches, including electric vehicle (EV) drivetrain, bidirectional EV chargers, industrial motor drives, solid-state transformers, datacenter power supplies, elevator drives, dc microgrids, energy storage grid integration, solid-state breakers, etc.}, number={1}, journal={IEEE POWER ELECTRONICS MAGAZINE}, author={Bhattacharya, Subhashish and Narwal, Ramandeep and Shah, Suyash Sushilkumar and Baliga, B. Jayant and Agarwal, Aditi and Kanale, Ajit and Han, Kijeong and Hopkins, Douglas C. and Cheng, Tzu-Hsuan}, year={2023}, month={Mar}, pages={39–43} }
 @article{baliga_hopkins_bhattacharya_agarwal_cheng_narwal_kanale_shah_han_2023, title={The BiDFET Device and Its Impact on Converters}, volume={10}, ISSN={["2329-9215"]}, url={https://doi.org/10.1109/MPEL.2023.3237059}, DOI={10.1109/MPEL.2023.3237059}, abstractNote={The matrix converter topology for direct ac-to-ac conversion offers elimination of the bulky and unreliable d.c. link capacitors used in the popular voltage-source inverter (VSI) with a front-end rectifier. The resulting more compact and higher efficiency implementation is a desirable solution for a wide variety of applications, such as photovoltaic energy generation, motor drives, and energy storage systems.}, number={1}, journal={IEEE POWER ELECTRONICS MAGAZINE}, author={Baliga, B. Jayant and Hopkins, Douglas and Bhattacharya, Subhashish and Agarwal, Aditi and Cheng, Tzu-Hsuan and Narwal, Ramandeep and Kanale, Ajit and Shah, Suyash Sushilkumar and Han, Kijeong}, year={2023}, month={Mar}, pages={20–27} }
 @article{agarwal_han_baliga_2021, title={650-V 4H-SiC Planar Inversion-Channel Power JBSFETs With 55-nm Gate Oxide: Relative Performance of Three Cell Types}, volume={68}, ISSN={["1557-9646"]}, DOI={10.1109/TED.2021.3067921}, abstractNote={Planar 650-V 4H-silicon carbide (SiC), inversion-channel, 55-nm gate oxide junction barrier Schottky field effect transistors (JBSFETs) with three types of cells are compared in this article for the first time. Devices with linear, hexagonal, and octagonal layouts were fabricated in a commercial foundry. The JBS diode was integrated within each cell type. The Schottky contact width for the JBS diode was adjusted to optimize third-quadrant ON-state voltage drop to below 2.5 V for each cell type to ensure by-passing the body diode while maintaining good blocking characteristics in the first quadrant. The hexagonal cell case was the only one whose breakdown voltage (560 V) fell below the 650-V rating. The highest breakdown voltage (710 V) was observed with the octagonal cell layout with a low leakage current of 10 nA at 600 V. The lowest specific ON-resistance was observed for the hexagonal cell design. However, its gate-drain charge was twice that of the conventional linear cell design and four times that of the octagonal cell design. The data from this work demonstrate that the best overall performance for the 650-V SiC, inversion-channel, 55-nm gate oxide junction barrier Schottky field effect transistors is achieved by using the octagonal cell design.}, number={5}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Agarwal, Aditi and Han, Kijeong and Baliga, B. J.}, year={2021}, month={May}, pages={2395–2400} }
 @article{agarwal_han_baliga_2021, title={Assessment of Linear, Hexagonal, and Octagonal Cell Topologies for 650 V 4H-SiC Inversion-Channel Planar-Gate Power JBSFETs Fabricated With 27 nm Gate Oxide Thickness}, volume={9}, ISSN={["2168-6734"]}, DOI={10.1109/JEDS.2020.3040353}, abstractNote={A 27 nm gate oxide thickness has been successfully used for manufacturing high performance 650V 4H-SiC planar-gate, inversion-channel power JBSFETs in a 6-inch commercial foundry with three (Linear, Hexagonal, and Octagonal) cell topologies. The 27 nm gate oxide thickness allows operation of these JBSFETs at a gate bias of 15 V compared with 20 V used in previous reports for devices with 55 nm gate oxide thickness. The width for the Schottky contact was varied to optimize the performance of the JBS diode in the third quadrant for each cell topology. An on-state voltage drop of 2.5 V or less was achieved in the third quadrant for all the cell topologies by current flow through the integrated JBS diode, satisfying the objective of effectively by-passing the MOSFET body diode. The best breakdown voltage was achieved using the Octagonal cell topology with a half-cell Schottky contact width of 1.1 μm . It had a breakdown voltage of 850 V with a low leakage current of less than 5 nA at 650 V. The Linear cell (with half-cell Schottky contact width of 1.0 μm) and the Octagonal cell (with half-cell Schottky contact width of 2.8 μm) had blocking voltages of 800 V. The hexagonal cell topology (with half-cell Schottky contact width of 1.5 μm) had the worst blocking voltage of 715 V. Numerical simulation results are provided to show that the leakage current in all cell topologies begins to increase when the electric field at the Schottky contact exceeds 1.5 MV/cm. The lowest specific on-resistance was obtained with the hexagonal cell topology but its gate-drain charge was 2× larger than the conventional Linear cell design. The Octagonal cell topology with half-cell Schottky contact width of 1.1 μm had the same specific on-resistance as the Linear cell case with 2× smaller gate-drain charge. This work demonstrates for the first time that excellent High-Frequency Figures-of-Merit can be achieved with a reduced gate drive voltage of 15 V for 650 V SiC JBSFETs by using a smaller gate oxide thickness of 27 nm and the Octagonal cell topology.}, journal={IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY}, author={Agarwal, Aditi and Han, Kijeong and Baliga, B. J.}, year={2021}, pages={79–88} }
 @inproceedings{kanale_cheng_shah_han_agarwal_baliga_hopkins_bhattacharya_2021, title={Switching Characteristics of a 1.2 kV, 50 mΩ SiC Monolithic Bidirectional Field Effect Transistor (BiDFET) with Integrated JBS Diodes}, ISBN={9781728189499}, ISSN={["1048-2334"]}, url={http://dx.doi.org/10.1109/apec42165.2021.9487410}, DOI={10.1109/APEC42165.2021.9487410}, abstractNote={The switching performance of large area (1cm x 1cm) monolithic 1.2 kV 50 mΩ 4H-SiC bidirectional field effect transistor (BiDFET) with integrated JBS diodes is reported for the first time. The devices were fabricated in a 6-inch commercial foundry and then packaged in a custom-designed four-terminal module. The switching performance of the BiDFET has been observed to be 1.4x better than that of its internal JBSFETs. Dynamic characterization was performed at 800 V with different gate resistances, current levels and case temperatures. An increase in switching losses was observed for the BiDFET with increasing gate resistance and current level as observed for SiC power MOSFETs. The BiDFET showed a 9% reduction in total switching loss from 25 °C to 150 °C with a current of 10 A.}, booktitle={2021 IEEE Applied Power Electronics Conference and Exposition (APEC)}, publisher={IEEE}, author={Kanale, Ajit and Cheng, Tzu-Hsuan and Shah, Suyash Sushilkumar and Han, Kijeong and Agarwal, Aditi and Baliga, B. Jayant and Hopkins, Douglas and Bhattacharya, Subhashish}, year={2021}, month={Jun}, pages={1267–1274} }
 @article{han_baliga_2020, title={1.2-kV 4H-SiC SenseFET With Monolithically Integrated Sensing Resistor}, volume={41}, ISSN={["1558-0563"]}, DOI={10.1109/LED.2020.2964773}, abstractNote={A 1.2 kV rated 4H-SiC SenseFET structure with monolithically integrated sensing resistor is proposed and experimentally demonstrated. The SenseFET was fabricated on a 6-inch SiC wafer using the same fabrication process as the conventional MOSFET, where Tungsten-Silicided (WSi2) Poly-Si layer was patterned to form the Poly-Si gate and sensing resistor, ${R}_{S}$ , simultaneously. No impact of the integration of the Sense MOSFET and sense resistor on blocking characteristics was confirmed. Good linearity (within ±10%) of the sense voltage with main MOSFET drain current was observed, independent of drain current level, gate bias voltage, and temperature.}, number={3}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Han, Kijeong and Baliga, B. J.}, year={2020}, month={Mar}, pages={437–440} }
 @article{agarwal_han_baliga_2020, title={2.3 kV 4H-SiC Accumulation-Channel Split-Gate Planar Power MOSFETs With Reduced Gate Charge}, volume={8}, ISSN={["2168-6734"]}, DOI={10.1109/JEDS.2020.2991355}, abstractNote={2.3 kV 4H-SiC split-gate (SG) planar accumulation-channel power MOSFETs have been successfully manufactured in a 6 inch commercial foundry with good parametric distributions. The measured electrical characteristics of these devices are compared with conventional ACCUFETs manufactured with the same cell-pitch and process to quantify the improved performance. The gate charge and high-frequency figures-of-merit (HF-FOM) of the 2.3 kV SG-MOSFETs were experimentally verified to be a factor of 1.8x better than that of the conventional MOSFETs with no difference in specific on-resistance.}, number={1}, journal={IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY}, author={Agarwal, Aditi and Han, Kijeong and Baliga, B. Jayant}, year={2020}, pages={499–504} }
 @article{agarwal_han_baliga_2020, title={2.3-kV, 5-A 4H-SiC Ti and Ni JBS Rectifiers manufactured in Commercial Foundry: Impact of Implant Lateral Straggle}, DOI={10.1109/WiPDAAsia49671.2020.9360272}, abstractNote={This paper reports characteristics of 2.3-kV 5-A 4H-SiC Junction Barrier controlled Schottky (JBS) rectifiers manufactured in a 6-inch commercial foundry. Two types (Ni and Ti Schottky contact metal) of JBS rectifiers were successfully fabricated. The electrical performance of the Ni and Ti JBS rectifiers is compared at temperatures up to 150°C. The on-state voltage drop (@ 5 A) of the Ti devices increased from 1.4 to 1.8 V with increasing temperature while that for Ni devices increased from 2.0 to 2.3 V, maintaining values well below that of the SiC P-N junction as required for a JBS diode. The leakage current for the Ni JBS diodes remained below 2 nA @ 500V even up to 150°C. In contrast, an increase in leakage current to an acceptable level of 100 nA @ 500V was observed for the Ti JBS diodes at 150°C due to its lower barrier height. Analytical modelling indicated that lateral straggle of the P <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> ion-implant plays an important role in determining the measured on-state voltage drop and reverse leakage characteristics. Simulations were performed to confirm the effect of lateral implant straggle. The simulations demonstrated that lateral implant straggle increases the on-resistance and reduces the leakage current of the JBS rectifier but has no effect on the knee voltage. The experimental results in this paper demonstrate that 4H-SiC JBS rectifiers with 2.3 kV blocking voltage can be manufactured using either Ni or Ti Schottky contacts with excellent on-state voltage drop and leakage current up to 150°C.}, journal={2020 IEEE WORKSHOP ON WIDE BANDGAP POWER DEVICES AND APPLICATIONS IN ASIA (WIPDA ASIA)}, author={Agarwal, Aditi and Han, Kijeong and Baliga, B. Jayant}, year={2020} }
 @article{agarwal_han_jayant baliga_2020, title={600 V 4H-SiC MOSFETs Fabricated in Commercial Foundry With Reduced Gate Oxide Thickness of 27 nm to Achieve IGBT-Compatible Gate Drive of 15 V (vol 40, pg 1792, 2019)}, volume={41}, ISSN={["1558-0563"]}, DOI={10.1109/LED.2019.2956966}, number={1}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Agarwal, Aditi and Han, Kijeong and Jayant Baliga, B.}, year={2020}, month={Jan}, pages={195–195} }
 @article{agarwal_han_baliga_2020, title={Comparison of 2.3-kV 4H-SiC Accumulation-Channel Planar Power MOSFETs Fabricated With Linear, Square, Hexagonal, and Octagonal Cell Topologies}, volume={67}, ISSN={["1557-9646"]}, DOI={10.1109/TED.2020.3005632}, abstractNote={The performance of four cell topologies is compared for 2.3-kV 4H-SiC power MOSFETs fabricated in a commercial 6-in foundry. The devices were simultaneously manufactured with the same channel length (0.5 $ {\mu } \text{m}$ ), JFET width (1.1 $ {\mu } \text{m}$ ), and gate oxide thickness (55 nm) for comparison. In addition, an octagonal cell design with a JFET width of 1.5 $ {\mu } \text{m}$ was included for comparison. The square and hexagonal cell designs had the lowest specific ON-resistance, but their breakdown voltage was found to be reduced below 2.3 kV due to sharp cell corners. The smallest reverse transfer capacitance and gate charge were observed for the octagonal cell design with significantly larger (~5 $\times $ ) values for the square and hexagonal designs. The high-frequency figure-of-merit HF-FOM[ ${R}_{\mathrm{\scriptscriptstyle ON}}{\ast } {C}_{\text {rss}}$ ] for the octagonal cell design was $3.5\times $ superior to the hexagonal and square cells and $1.5\times $ better than the linear cell. Its high-frequency figure-of-merit HF-FOM[ ${R}_{\mathrm{\scriptscriptstyle ON}} {\ast } {Q}_{\text {gd}}$ ] was $1.5\times $ superior to the hexagonal and square cells and $1.2\times $ better than the linear cell. This work demonstrates that the square and hexagonal cells are the best for low-frequency applications, whereas the octagonal cell design is the most suitable for achieving the best high-frequency performance of 2.3-kV 4H-SiC power MOSFETs.}, number={9}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Agarwal, Aditi and Han, Kijeong and Baliga, B. J.}, year={2020}, pages={3673–3678} }
 @article{agarwal_han_baliga_2019, title={600 V 4H-SiC MOSFETs Fabricated in Commercial Foundry With Reduced Gate Oxide Thickness of 27 nm to Achieve IGBT-Compatible Gate Drive of 15 V}, volume={40}, ISSN={["1558-0563"]}, DOI={10.1109/LED.2019.2942259}, abstractNote={The measured electrical characteristics of 600 V planar-gate inversion-channel 4H-SiC power MOSFETs fabricated in a 6 inch commercial foundry with 27 nm gate oxide thickness are compared with 55 nm gate oxide devices. The High-Frequency Figures-of-Merit (HF-FOMs) of the SiC MOSFETs with 27 nm gate oxide were found to surpass that of commercially available 600 V P7 Si CoolMOS products for the first time. Statistical parametric distribution data and wafer-maps for the 27 nm devices are provided to demonstrate that excellent yield and uniformity can be achieved with the reduced gate oxide thickness. These devices can be operated at 15 V gate bias compatible with IGBT gate drivers.}, number={11}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Agarwal, Aditi and Han, Kijeong and Baliga, B. Jayant}, year={2019}, month={Nov}, pages={1792–1795} }
 @article{han_baliga_2019, title={Analysis and Experimental Quantification of 1.2-kV 4H-SiC Split-Gate Octagonal MOSFET}, volume={40}, ISSN={["1558-0563"]}, DOI={10.1109/LED.2019.2917637}, abstractNote={A1.2-kV rated 4H-SiC split-gate octagonal cell MOSFET (SG-OCTFET) is proposed and successfully fabricated in a 6-in foundry for the first time. The measured results quantify the benefits of the SG-OCTFET structure: improvement in high-frequency figures of merit (HF-FOM) (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> × C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> ) by 1.8×, HF-FOM (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> × Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> ) by 1.6×, and FOM (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">iss</sub> /C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> ) by 1.6× compared with the optimized compact OCTFET design due to the reduced gate-to-drain overlap area. An important conclusion of this letter is that unlike commercially available 1.2-kV SiC power MOSFETs with linear cell topology, the 1.2-kV SG-OCTFET design can outperform commercially available 600-V Si super-junction devices.}, number={7}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Han, Kijeong and Baliga, B. J.}, year={2019}, month={Jul}, pages={1163–1166} }
 @article{han_baliga_2019, title={Comparison of Four Cell Topologies for 1.2-kV Accumulation- and Inversion-Channel 4H-SiC MOSFETs: Analysis and Experimental Results}, volume={66}, ISSN={["1557-9646"]}, DOI={10.1109/TED.2019.2905736}, abstractNote={The electrical characteristics of 1.2-kV-rated 4H-SiC accumulation (Acc) and inversion (Inv) channel MOSFETs with linear, square, hexagonal, and octagonal cell topologies fabricated using the same design rules and process flow in a 6-in foundry are compared for the first time. TCAD numerical simulations have been conducted to analyze the structures. For all the cell topologies, it was found that the Acc MOSFETs have lower specific ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ ) than the Inv counterparts due to higher channel mobility resulting in 1.3– $2.0\times $ smaller high-frequency figure-of-merit (HF-FOM[ ${R} _{ \mathrm{\scriptscriptstyle ON}} \times {Q}_{\textsf {gd}}$ ]), where ${Q} _{\textsf {gd}}$ is the gate-to-drain charge. It is observed that the square and hexagonal cell topologies with the same structural dimensions show similar electrical performance. When compared with the standard linear cell topology: 1) the hexagonal cell topology has $1.15\times $ better specific ON-resistance and $1.12\times $ worse HF-FOM[ $\text{R}_{ \mathrm{\scriptscriptstyle ON}} \times {Q}_{\textsf {gd}}$ ] and 2) the octagonal cell topology has $1.5\times $ worse specific ON-resistance and $1.4\times $ better HF-FOM[ $\text{R}_{ \mathrm{\scriptscriptstyle ON}} \times {Q}_{\textsf {gd}}$ ]. In addition, the octagonal cell topology has a much superior figure-of-merit (FOM[ ${C} _{\textsf {iss}}/{C} _{\textsf {rss}}$ ]), where ${C} _{\textsf {iss}}$ is the input capacitance and ${C} _{\textsf {gd}}$ is the reverse transfer capacitance.}, number={5}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Han, Kijeong and Baliga, B. J.}, year={2019}, month={May}, pages={2321–2326} }
 @article{han_baliga_2019, title={Comprehensive Physics of Third Quadrant Characteristics for Accumulation- and Inversion-Channel 1.2-kV 4H-SiC MOSFETs}, volume={66}, ISSN={["1557-9646"]}, DOI={10.1109/TED.2019.2929733}, abstractNote={Detailed physics of the third quadrant electrical characteristics of 1.2-kV rated 4H-SiC accumulation (Acc) and inversion (Inv) channel MOSFETs, based on experimentally measured data and TCAD numerical simulations, are described in this paper for the first time. The power MOSFETs with various channel lengths (0.3, 0.5, 0.8, 1.1 μm) used in this paper were fabricated in a 6-in commercial foundry. Numerical simulations verified that there are two current paths in the third quadrant: 1) through the base region and 2) through the p-n body diode. This paper demonstrates that the Acc MOSFETs have a smaller third quadrant knee voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">knee</sub> ) of -1.2 V compared with -1.9 V for the Inv MOSFETs (at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> = 0V and room temperature). Numerical simulations show that this difference is due to a smaller potential barrier for electron transport from the drain to the source in the base region for accumulation channel devices than inversion channel devices. Acc devices are shown to have a lower voltage drop in the third quadrant.}, number={9}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Han, Kijeong and Baliga, B. J.}, year={2019}, month={Sep}, pages={3923–3928} }
 @article{agarwal_han_baliga_2019, title={Impact of Cell Topology on Characteristics of 600V 4H-SiC Planar MOSFETs}, volume={40}, ISSN={["1558-0563"]}, DOI={10.1109/LED.2019.2908078}, abstractNote={This letter compares the measured electrical characteristics of 600 V planar-gate inversion-channel 4H-SiC power MOSFETs fabricated with four different cell topologies (Linear, Square, Hexagonal, and Octagonal) for the first time. The High-Frequency Figures-of-Merit (HF-FOMs) of these devices were compared with the commercially available SiC device and the Si CoolMOS product. It was found that the HF-FOMs of the 600-V SiC product and our fabricated conventional Linear cell device are much worse in comparison to the Si CoolMOS product. However, the 600 V SiC power MOSFET with comparable performance to the Si CoolMOS product could be achieved by using the Octagonal cell topology.}, number={5}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Agarwal, Aditi and Han, Kijeong and Baliga, B. Jayant}, year={2019}, month={May}, pages={773–776} }
 @article{han_baliga_2019, title={The 1.2-kV 4H-SiC OCTFET: A New Cell Topology With Improved High-Frequency Figures-of-Merit}, volume={40}, ISSN={["1558-0563"]}, DOI={10.1109/LED.2018.2889221}, abstractNote={A 1.2 kV rated 4H-SiC OCTFET device with octagonal-cell topology is proposed and experimentally demonstrated for the first time. The device was first optimized using TCAD numerical simulations. Devices were then successfully fabricated in a 6-inch foundry. From the measured electrical characteristics, the OCTFET is demonstrated to have 1.4x superior high frequency figures-ofmerits (HF-FOM) [R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> × Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> ], and 2.1× superior HF-FOM [R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> × C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> ] compared with the conventional linear-cell MOSFET.}, number={2}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Han, Kijeong and Baliga, B. J.}, year={2019}, month={Feb}, pages={299–302} }
 @article{han_baliga_sung_2018, title={A Novel 1.2 kV 4H-SiC Buffered-Gate (BG) MOSFET: Analysis and Experimental Results}, volume={39}, ISSN={["1558-0563"]}, DOI={10.1109/led.2017.2785771}, abstractNote={A novel 1.2-kV-rated 4H-SiC buffered-gate MOSFET (BG-MOSFET) structure is proposed and experimentally demonstrated to have superior high frequency figures-of-merit (HF-FOMs) for the first time. From the measured data on devices fabricated in a 6-in foundry, the BGMOSFET is demonstrated to have 4.0× and 2.6× smaller HF-FOM [R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> × Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> ], and 3.6× and 2.1× smaller HF-FOM [R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> × C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> ], when compared with the conventional MOSFET and split-gate MOSFET, respectively.}, number={2}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Han, Kijeong and Baliga, B. J. and Sung, Woongje}, year={2018}, month={Feb}, pages={248–251} }
 @inproceedings{raheja_gohil_han_acharya_baliga_battacharya_labreque_smith_lal_2017, title={Applications and characterization of four quadrant GaN switch}, volume={2017-January}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85041481367&partnerID=MN8TOARS}, DOI={10.1109/ecce.2017.8096397}, abstractNote={Bi-directional switches, also called four quadrant switches (FQS), are the basic building blocks in many power converter circuits, such as cyclo-converters, matrix converters etc. Conventional approaches to realize bi-directional switch involves combination of unidirectional controllable blocking device (IGBT or MOSFET) and diode. In this approach, current flows through multiple devices for any direction of current flow. This leads to higher conduction losses. Moreover, use of multiple devices increases system size. The die size and semiconductor losses can be reduced by realizing a bi-directional switch using a single die. Further improvement can be achieved by using Gallium Nitride (GaN) semiconductor. This paper discusses characterization of such a four quadrant GaN switch, made using a single die. Static characterization is performed, where the on-state resistances are obtained along with the output characteristics. A double pulse test setup has been built for characterizing FQS's and the experiments were performed to obtain the turn-on and turn-off switching energies.}, booktitle={2017 ieee energy conversion congress and exposition (ecce)}, author={Raheja, U. and Gohil, G. and Han, K. and Acharya, Sayan and Baliga, B. J. and Battacharya, S. and Labreque, M. and Smith, P. and Lal, R.}, year={2017}, pages={1967–1974} }
 @article{han_baliga_sung_2017, title={Split-gate 1.2-kV 4H-SiC MOSFET: Analysis and experimental validation}, volume={38}, DOI={10.1109/led.2017.2738616}, abstractNote={The 1.2-kV-rated 4H-SiC Split Gate MOSFET (SG-MOSFET) structure is demonstrated to have a superior high-frequency figures-of-merit (HF-FOMs) by numerical simulations, with experimental validation for the first time. Excellent electrical characteristics (specific on-resistance, threshold voltage, breakdown voltage, reverse transfer capacitance,and gate-todrain charge) were measured from devices fabricated on a 6-in SiC wafer. Compared with the conventional MOSFET, the SG-MOSFET has 2.4× smaller HF-FOM [R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> ×Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> ] due to the reduced gate-to-drain charge.}, number={10}, journal={IEEE Electron Device Letters}, author={Han, K. and Baliga, B. J. and Sung, W.}, year={2017}, pages={1437–1440} }
 @inproceedings{sung_han_baliga, title={Optimization of the JFET region of 1.2kV SiC MOSFETs for improved high frequency figure of merit (HF-FOM)}, booktitle={2017 IEEE 5th Workshop on Wide Bandgap Power Devices and Applications (WIPDA)}, author={Sung, W. J. and Han, K. J. and Baliga, B. J.}, pages={238–241} }