1998 conference paper
Evaluation and comparison of 3.0 nm gate-stack dielectrics for tenth-micron technology NMOSFETs
Rapid thermal and integrated processing VII: Symposium held April 13-15, 1998, San Francisco, California, U.S.A. (Materials Research Society symposium proceedings ; v.525), 157–162. Warrendale, Pennsylvania: Materials Research Society.
1998 conference paper
Evaluation of 2.0 nm grown and deposited dielectrics in 0.1 ?m PMOSFETs
Rapid thermal and integrated processing VII: Symposium held April 13-15, 1998, San Francisco, California, U.S.A. (Materials Research Society symposium proceedings ; v.525), 163–170.
1998 journal article
Parasitic resistance considerations of using elevated source/drain technology for deep submicron metal oxide semiconductor field effect transistors
Journal of the Electrochemical Society, 145(6), 2131–2137.
1997 conference paper
A 0.18 ?m CMOS technology for elevated source/drain MOSFETs using selective silicon epitaxy
ULSI science and technology/1997: Proceedings of the Sixth International Symposium on UltraLarge Scale Integration Science and Technology (Proceedings (Electrochemical Society); v. 97-3), 571–585. Pennington, NJ: Electrochemical Society.
1997 journal article
A comparative study of N+/p junction formation for deep submicron elevated source/drain metal oxide semiconductor field effect transistors
Journal of the Electrochemical Society, 144(10), 3659–3664.
1997 conference paper
Parasitic resistance considerations of using elevated source/drain for deep submicron MOSFET technology
ULSI science and technology/1997: Proceedings of the Sixth International Symposium on UltraLarge Scale Integration Science and Technology (Proceedings (Electrochemical Society); v. 97-3), 587–597. Pennington, NJ: Electrochemical Society.
1997 journal article
The effect of the elevated source/drain doping profile on performance and reliability of deep submicron MOSFET's
IEEE Transactions on Electron Devices, 44(9), 1491–1498.
1996 conference paper
Sub-half micron elevated source/drain NMOSFETs by low temperature selective epitaxial deposition
Rapid thermal and integrated processing V: Symposium held April 8-12, 1996, San Francisco, California, U.S.A. (Materials Research Society symposium; 429), 343–347.
1995 journal article
Effects of profile doped elevated source/drain structures on deep-submicron MOSFETs
Solid-State Electronics, 38(3), 573–579.
1994 journal article
An evaluation of super-steep-retrograde channel doping for deep-submicron MOSFET applications
IEEE Transactions on Electron Devices, 41(10), 1880–1882.
1994 journal article
Single wafer process integration for submicron structures
Journal of Vacuum Science & Technology, 12(4), 2749–2751.
1993 journal article
Center for Advanced Electronic Materials Processing
Proceedings of the IEEE, 81(1), 42–59.