Nino A. Masnari

Evaluation and comparison of 3.0 nm gate-stack dielectrics for tenth-micron technology NMOSFETs

Rapid thermal and integrated processing VII: Symposium held April 13-15, 1998, San Francisco, California, U.S.A. (Materials Research Society symposium proceedings ; v.525), 157–162. Warrendale, Pennsylvania: Materials Research Society.

Evaluation of 2.0 nm grown and deposited dielectrics in 0.1 mu m PMOSFETs

RAPID THERMAL AND INTEGRATED PROCESSING VII, Vol. 525, pp. 163–170.

Parasitic resistance considerations of using elevated source/drain technology for deep submicron metal oxide semiconductor field effect transistors

JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 145(6), 2131–2137.

A 0.18 ?m CMOS technology for elevated source/drain MOSFETs using selective silicon epitaxy

ULSI science and technology/1997: Proceedings of the Sixth International Symposium on UltraLarge Scale Integration Science and Technology (Proceedings (Electrochemical Society); v. 97-3), 571–585. Pennington, NJ: Electrochemical Society.

A comparative study of n(+)/p junction formation for deep submicron elevated source/drain metal oxide semiconductor field effect transistors

JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 144(10), 3659–3664.

Parasitic resistance considerations of using elevated source/drain for deep submicron MOSFET technology

ULSI science and technology/1997: Proceedings of the Sixth International Symposium on UltraLarge Scale Integration Science and Technology (Proceedings (Electrochemical Society); v. 97-3), 587–597. Pennington, NJ: Electrochemical Society.

The effect of the elevated source drain doping profile on performance and reliability of deep submicron MOSFET's

IEEE TRANSACTIONS ON ELECTRON DEVICES, 44(9), 1491–1498.

Sub-half micron elevated source/drain NMOSFETs by low temperature selective epitaxial deposition

RAPID THERMAL AND INTEGRATED PROCESSING V, Vol. 429, pp. 343–347.

Effects of profile doped elevated source/drain structures on deep-submicron MOSFETs

Solid-State Electronics, 38(3), 573–579.

An evaluation of super-steep-retrograde channel doping for deep-submicron MOSFET applications

IEEE Transactions on Electron Devices, 41(10), 1880–1882.

SINGLE-WAFER PROCESS INTEGRATION FOR SUBMICRON STRUCTURES

JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, Vol. 12, pp. 2749–2751.

CENTER FOR ADVANCED ELECTRONIC MATERIALS PROCESSING

PROCEEDINGS OF THE IEEE, 81(1), 42–59.