Works (6)

2013 conference paper

Hetero(2) 3d integration: A scheme for optimizing efficiency/cost of chip multiprocessors

Proceedings of the fourteenth international symposium on quality electronic design (ISQED 2013), 1–7.

By: S. Priyadarshi, N. Choudhary, B. Dwiel, A. Upreti, E. Rotenberg, R. Davis, P. Franzon

Source: NC State University Libraries
Added: August 6, 2018

2012 journal article

Efficiently exploiting memory level parallelism on asymmetric coupled cores in the dark silicon era

ACM Transactions on Architecture and Code Optimization, 8(4).

By: G. Patsilaras, N. Choudhary & J. Tuck

Source: NC State University Libraries
Added: August 6, 2018

2012 journal article

Fabscalar: Automating superscalar core design

IEEE Micro, 32(3), 48–59.

By: N. Choudhary, S. Wadhavkar, T. Shah, H. Mayukh, J. Gandhi, B. Dwiel, S. Navada, H. Najaf-Abadi, E. Rotenberg

Source: NC State University Libraries
Added: August 6, 2018

2011 journal article

FabScalar: Composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template

ISCA 2011: Proceedings of the 38th Annual International Symposium on Computer Architecture, 11–22.

By: N. Choudhary, S. Wadhavkar, T. Shah, H. Mayukh, J. Gandhi, B. Dwiel, S. Navada, H. Najaf-abadi, E. Rotenberg

Source: NC State University Libraries
Added: August 6, 2018

2010 conference paper

Criticality-driven superscalar design space exploration

Pact 2010: Proceedings of the Nineteenth International Conference on Parallel Architectures and Compilation Techniques, 261–272.

By: S. Navada, N. Choudhary & E. Rotenberg

Source: NC State University Libraries
Added: August 6, 2018

2009 conference paper

Core-selectability in chip multiprocessors

International conference on parallel architectures and compilation, 113–122.

By: H. Najaf-Abadi, N. Choudhary & E. Rotenberg

Source: NC State University Libraries
Added: August 6, 2018