Works (6)
Updated: July 5th, 2023 15:49
2013 conference paper
Hetero(2) 3d integration: A scheme for optimizing efficiency/cost of chip multiprocessors
Proceedings of the fourteenth international symposium on quality electronic design (ISQED 2013), 1–7.
Event: International Symposium on Quality Electronic Design (ISQED) at Santa Clara, CA on March 4-6, 2013
TL;DR:
This work proposes exploiting two complementary forms of heterogeneity to profitably exploit an immature technology for Chip Multiprocessors (CMP): 3D integration facilitates a technology alloy and application and microarchitectural heterogeneity is exploited to compensate for lower efficiency of old-technology cores.
(via Semantic Scholar)
Sources: NC State University Libraries, NC State University Libraries
Added: August 6, 2018
2012 journal article
Efficiently Exploiting Memory Level Parallelism on Asymmetric Coupled Cores in the Dark Silicon Era
ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 8(4).
author keywords: Design; Performance; Memory level parallelism; multicore; asymmetric multicore processor; dark silicon
TL;DR:
This work quantifies the potential for exploiting core customization to speedup programs during regions of high MLP and proposes a hardware-level, application steering mechanism called Symbiotic Core Execution (SCE), which yields an important message for designing AMPs with specialized cores.
(via Semantic Scholar)
open access via dl.acm.org (publisher PDF)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy
(OpenAlex)
Source: Web Of Science
Added: August 6, 2018
2012 journal article
FABSCALAR: AUTOMATING SUPERSCALAR CORE DESIGN
IEEE MICRO, 32(3), 48–59.
TL;DR:
FabScalar aims to automate superscalar core design, opening up processor design to microarchitectural diversity and its many opportunities.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy
(OpenAlex)
Source: Web Of Science
Added: August 6, 2018
2011 journal article
FabScalar: Composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template
ISCA 2011: Proceedings of the 38th Annual International Symposium on Computer Architecture, 11–22.
TL;DR:
From this idea, a toolset is developed, called FabScalar, for automatically composing the synthesizable register-transfer-level (RTL) designs of arbitrary cores within a canonical superscalar template, which defines canonical pipeline stages and interfaces among them.
(via Semantic Scholar)
Source: NC State University Libraries
Added: August 6, 2018
2010 article
Criticality-driven Superscalar Design Space Exploration
PACT 2010: PROCEEDINGS OF THE NINETEENTH INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES, pp. 261–272.
author keywords: design space exploration; criticality model; bottleneck analysis; superscalar processors; simulated annealing
TL;DR:
It has become increasingly difficult to perform design space exploration (DSE) of computer systems with a short turnaround time because of exploding design spaces, increasing design complexity and long-running workloads.
(via Semantic Scholar)
Source: Web Of Science
Added: August 6, 2018
2009 article
Core-Selectability in Chip Multiprocessors
18TH INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES, PROCEEDINGS, pp. 113–122.
author keywords: Chip Multiprocessor; Heterogeneity; Microarchitecture
TL;DR:
This paper proposes core-selectability – incorporating differently-designed cores that can be toggled into active employment that enables differently customized ILP-extracting structures to be at hand in the system while not dramatically adding to the interconnect complexity.
(via Semantic Scholar)
Source: Web Of Science
Added: August 6, 2018
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