Works (6)

Updated: July 5th, 2023 15:49

2013 conference paper

Hetero(2) 3d integration: A scheme for optimizing efficiency/cost of chip multiprocessors

Proceedings of the fourteenth international symposium on quality electronic design (ISQED 2013), 1–7.

By: S. Priyadarshi n, N. Choudhary n, B. Dwiel n, A. Upreti n, E. Rotenberg n, R. Davis n, P. Franzon n

Event: International Symposium on Quality Electronic Design (ISQED) at Santa Clara, CA on March 4-6, 2013

Sources: NC State University Libraries, ORCID
Added: August 6, 2018

2012 journal article

Efficiently Exploiting Memory Level Parallelism on Asymmetric Coupled Cores in the Dark Silicon Era

ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 8(4).

By: G. Patsilaras n, N. Choudhary n & J. Tuck n

author keywords: Design; Performance; Memory level parallelism; multicore; asymmetric multicore processor; dark silicon
Source: Web Of Science
Added: August 6, 2018

2012 journal article

FABSCALAR: AUTOMATING SUPERSCALAR CORE DESIGN

IEEE MICRO, 32(3), 48–59.

By: N. Choudhary n, S. Wadhavkar n, T. Shah n, H. Mayukh n, J. Gandhi n, B. Dwiel n, S. Navada n, H. Najaf-Abadi n, E. Rotenberg n

Source: Web Of Science
Added: August 6, 2018

2011 journal article

FabScalar: Composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template

ISCA 2011: Proceedings of the 38th Annual International Symposium on Computer Architecture, 11–22.

By: N. Choudhary n, S. Wadhavkar n, T. Shah*, H. Mayukh*, J. Gandhi*, B. Dwiel n, S. Navada n, H. Najaf-abadi*, E. Rotenberg n

Source: NC State University Libraries
Added: August 6, 2018

2010 article

Criticality-driven Superscalar Design Space Exploration

PACT 2010: PROCEEDINGS OF THE NINETEENTH INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES, pp. 261–272.

By: S. Navada n, N. Choudhary n & E. Rotenberg n

author keywords: design space exploration; criticality model; bottleneck analysis; superscalar processors; simulated annealing
Source: Web Of Science
Added: August 6, 2018

2009 article

Core-Selectability in Chip Multiprocessors

18TH INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES, PROCEEDINGS, pp. 113–122.

By: H. Najaf-abadi n, N. Choudhary n & E. Rotenberg n

author keywords: Chip Multiprocessor; Heterogeneity; Microarchitecture
Source: Web Of Science
Added: August 6, 2018

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