Works (6)
2013 conference paper
Hetero(2) 3d integration: A scheme for optimizing efficiency/cost of chip multiprocessors
Proceedings of the fourteenth international symposium on quality electronic design (ISQED 2013), 1–7.
2012 journal article
Efficiently Exploiting Memory Level Parallelism on Asymmetric Coupled Cores in the Dark Silicon Era
ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 8(4).

2012 journal article
FABSCALAR: AUTOMATING SUPERSCALAR CORE DESIGN
IEEE MICRO, 32(3), 48–59.

2011 journal article
FabScalar: Composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template
ISCA 2011: Proceedings of the 38th Annual International Symposium on Computer Architecture, 11–22.
2010 article
Criticality-driven Superscalar Design Space Exploration
PACT 2010: PROCEEDINGS OF THE NINETEENTH INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES, pp. 261–272.
2009 article
Core-Selectability in Chip Multiprocessors
18TH INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES, PROCEEDINGS, pp. 113–122.