Works (10)

Updated: July 5th, 2023 15:46

2016 journal article

Physical understanding of trends in current collapse with atomic layer deposited dielectrics in AlGaN/GaN MOS heterojunction FETs

SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 31(3).

By: N. Ramanan n, B. Lee n & V. Misra n

author keywords: heterojunctions; power transistors; semiconductor-insulator interfaces; semiconductor device reliability; high-k gate dielectrics; atomic layer deposition; AlGaN/GaN
Sources: Web Of Science, ORCID
Added: August 6, 2018

2015 journal article

ALD gate dielectrics for improved threshold voltage stability in AlGaN/GaN MOS-HFETs for power applications

SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 30(12).

By: N. Ramanan n, B. Lee n & V. Misra n

author keywords: power transistors; semiconductor-insulator interfaces; semiconductor device reliability; high-k gate dielectrics; atomic layer deposition (ALD); AlGaN/GaN; MOSHFET
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (OpenAlex)
Sources: Web Of Science, ORCID
Added: August 6, 2018

2015 journal article

Accurate characterization and understanding of interface trap density trends between atomic layer deposited dielectrics and AlGaN/GaN with bonding constraint theory

Applied Physics Letters, 106(24), 243503.

By: N. Ramanan n, B. Lee n & V. Misra n

Sources: NC State University Libraries, ORCID, Crossref
Added: August 6, 2018

2015 journal article

Comparison of Methods for Accurate Characterization of Interface Traps in GaN MOS-HFET Devices

IEEE TRANSACTIONS ON ELECTRON DEVICES, 62(2), 546–553.

By: N. Ramanan n, B. Lee n & V. Misra n

author keywords: Heterojunctions; millimeter wave transistors; power transistors; semiconductor device reliability; semiconductor-insulator interfaces
Sources: Web Of Science, ORCID
Added: August 6, 2018

2014 conference paper

A novel methodology using pulsed-IV for interface or border traps characterization on AlGaN/GaN MOSHFETs

Proceedings of the international symposium on power semiconductor, 366–369.

By: N. Ramanan n, B. Lee n & V. Misra n

Sources: NC State University Libraries, ORCID
Added: August 6, 2018

2014 journal article

Device Modeling for Understanding AlGaN/GaN HEMT Gate-Lag

IEEE TRANSACTIONS ON ELECTRON DEVICES, 61(6), 2012–2018.

By: N. Ramanan n, B. Lee n & V. Misra n

author keywords: AlGaN/GaN; current collapse; gate-lag; HEMT; high electron mobility transistor; passivation; reliability
Sources: Web Of Science, ORCID
Added: August 6, 2018

2014 journal article

Dual Floating Gate Unified Memory MOSFET With Simultaneous Dynamic and Non-Volatile Operation

IEEE ELECTRON DEVICE LETTERS, 35(1), 48–50.

By: B. Sarkar n, N. Ramanan n, S. Jayanti n, N. Di Spigna n, B. Lee n, P. Franzon n, V. Misra n

author keywords: Flash memory; floating gate; dynamic memory; MOSFET; FN tunneling; direct tunneling
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (OpenAlex)
Sources: Web Of Science, ORCID
Added: August 6, 2018

2014 article

Flash MOS-HFET operational stability for power converter circuits

PHYSICA STATUS SOLIDI C: CURRENT TOPICS IN SOLID STATE PHYSICS, VOL 11, NO 3-4, Vol. 11, pp. 875–878.

By: C. Kirkpatrick n, B. Lee n, N. Ramanan n & V. Misra n

author keywords: MOSHFET; flash; ALD; power converter
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (OpenAlex)
Sources: Web Of Science, ORCID
Added: August 6, 2018

2013 journal article

Properties of atomic layer deposited dielectrics for AlGaN/GaN device passivation

SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 28(7).

By: N. Ramanan n, B. Lee n, C. Kirkpatrick n, R. Suri n & V. Misra n

Sources: Web Of Science, ORCID
Added: August 6, 2018

2011 journal article

Multivalued Logic Using a Novel Multichannel GaN MOS Structure

IEEE ELECTRON DEVICE LETTERS, 32(10), 1379–1381.

By: N. Ramanan n & V. Misra n

author keywords: Gallium nitride; heterostructure; MOS device; multichannel; multivalued logic (MVL); quaternary logic
TL;DR: This letter presents a novel charge-based multistate transistor device on the AlGaN/GaN system which uses a given gate length but handles more than two states any time, and proposes architectures for the implementation of some basic quaternary logic gates. (via Semantic Scholar)
Sources: Web Of Science, ORCID
Added: August 6, 2018

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