Ralph K. Cavin, III

Integrated circuit devices having on-chip adaptive bandwidth buses and related methods

Washington, DC: U.S. Patent and Trademark Office.

A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12(8), 876–880.

Current-mode signaling in deep submicrometer global interconnects

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 11(3), 406–417.

CMOS high-speed data recovery circuit using the matched delay sampling technique

IEEE Journal of Solid-State Circuits, 32(10), 1588–1596.

The delay Vernier pattern generation technique

IEEE Journal of Solid-State Circuits, 32(4), 551–562.

Method and apparatus for high speed digital sampling of a data signal

Washington, DC: U.S. Patent and Trademark Office.