Works (6)
Updated: July 5th, 2023 16:04
2006 patent
Integrated circuit devices having on-chip adaptive bandwidth buses and related methods
Washington, DC: U.S. Patent and Trademark Office.
Source: NC State University Libraries
Added: August 6, 2018
2004 journal article
A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 12(8), 876–880.
author keywords: adaptive; bus; current-mode (CM); on-chip interconnects; repeater
TL;DR:
An adaptive bandwidth bus architecture based on hybrid current/voltage mode repeaters for long global RC interconnect static busses that achieves high-data rates while minimizing the static power dissipation associated with current-mode (CM) signaling is described.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy
(OpenAlex)
Source: Web Of Science
Added: August 6, 2018
2003 journal article
Current-mode signaling in deep submicrometer global interconnects
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 11(3), 406–417.
author keywords: current-mode; delay; interconnect; on-chip signaling; repeater
TL;DR:
A new closed-form solution of delay under step input excitation for current mode signaling in deep submicrometer global interconnects and a new power-dissipation model for current-mode signaling is developed to understand the design tradeoffs between current and voltage sensing.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy
(OpenAlex)
Source: Web Of Science
Added: August 6, 2018
1997 journal article
A CMOS high-speed data recovery circuit using the matched delay sampling technique
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 32(10), 1588–1596.
author keywords: clock and data recovery; NRZ data; DLL; transceiver
TL;DR:
This paper presents a scheme and circuitry for demultiplexing and synchronizing high-speed serial data using the matched delay sampling technique and achieves a very fine sampling resolution which is determined by the difference between the data and clock delays.
(via Semantic Scholar)
citeseerx.ist.psu.edu (repository)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy
(OpenAlex)
Source: Web Of Science
Added: August 6, 2018
1997 journal article
The delay vernier pattern generation technique
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 32(4), 551–562.
author keywords: delay circuits; delay-locked loops; delay verniers; signal generators; wave pipelining
TL;DR:
A new technique for generating an arbitrary digital data stream with very fine timing resolution, called the delay vernier generator, which can achieve unprecedented timing resolution in a particular circuit technology.
(via Semantic Scholar)
Source: Web Of Science
Added: August 6, 2018
1993 patent
Method and apparatus for high speed digital sampling of a data signal
Washington, DC: U.S. Patent and Trademark Office.
Source: NC State University Libraries
Added: August 6, 2018
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