@misc{integrated circuit devices having on-chip adaptive bandwidth buses and related methods_2006, volume={7,110,420}, publisher={Washington, DC: U.S. Patent and Trademark Office}, year={2006} }
 @article{bashirullah_liu_cavin_edwards_2004, title={A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability}, volume={12}, ISSN={["1557-9999"]}, DOI={10.1109/tvlsi.2004.831481}, abstractNote={This brief describes an adaptive bandwidth bus architecture based on hybrid current/voltage mode repeaters for long global RC interconnect static busses that achieves high-data rates while minimizing the static power dissipation associated with current-mode (CM) signaling. An experimental adaptive bandwidth bus test chip fabricated in AMI 1.6-/spl mu/m Bulk CMOS indicates a reduction in power dissipation of approximately 62% over CM sensing and an increase in maximum data rate of 40% over voltage-mode signaling.}, number={8}, journal={IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS}, author={Bashirullah, R and Liu, WT and Cavin, R and Edwards, D}, year={2004}, month={Aug}, pages={876–880} }
 @article{bashirullah_liu_cavin_2003, title={Current-mode signaling in deep submicrometer global interconnects}, volume={11}, ISSN={["1557-9999"]}, DOI={10.1109/TVLSI.2003.812366}, abstractNote={This paper addresses propagation delay and power dissipation for current mode signaling in deep submicrometer global interconnects. Based on the effective lumped element resistance and capacitance approximation of distributed RC lines, simple yet accurate closed-form expressions of delay and power dissipation are presented. A new closed-form solution of delay under step input excitation is first developed, exhibiting an accuracy that is within 5% of SPICE simulations for a wide range of parameters. The usefulness of this solution is that resistive load termination for current mode signaling is accurately modeled. This model is then extended to a generalized delay formulation for ramp inputs with arbitrary rise time. Using these expressions, the optimum-line width that minimizes the total delay for current mode circuits is found. Additionally, a new power-dissipation model for current-mode signaling is developed to understand the design tradeoffs between current and voltage sensing. Based on the results and derived formulations, a comparison between voltage and current mode repeater insertion for long global deep submicrometer interconnects is presented.}, number={3}, journal={IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS}, author={Bashirullah, R and Liu, WT and Cavin, RK}, year={2003}, month={Jun}, pages={406–417} }
 @article{kang_liu_cavin_1997, title={A CMOS high-speed data recovery circuit using the matched delay sampling technique}, volume={32}, ISSN={["0018-9200"]}, DOI={10.1109/4.634670}, abstractNote={This paper presents a scheme and circuitry for demultiplexing and synchronizing high-speed serial data using the matched delay sampling technique. By simultaneously propagating data and clock signals through two different delay taps, the sampler achieves a very fine sampling resolution which is determined by the difference between the data and clock delays. This high resolution sampling capability of the matched delay sampler can be used in the oversampling data recovery circuit. A data recovery circuit using the matched delay sampling technique has been designed and fabricated in 1.2-/spl mu/m CMOS technology. The chip has been tested at 417 Mb/s [2.4 ns nonreturn to zero (NRZ)] input data and demultiplexes serial input data into four 104 Mb/s (9.6 ns NRZ) output streams with 800 mW power consumption at 4 V power supply. While recovering data, the sampling clock running at 1/4 of the data frequency is phase-tracking with the input data based on information extracted from a digital phase control circuit.}, number={10}, journal={IEEE JOURNAL OF SOLID-STATE CIRCUITS}, author={Kang, JK and Liu, WT and Cavin, RK}, year={1997}, month={Oct}, pages={1588–1596} }
 @article{moyer_clements_liu_schaffer_cavin_1997, title={The delay vernier pattern generation technique}, volume={32}, ISSN={["0018-9200"]}, DOI={10.1109/4.563677}, abstractNote={The authors describe a new technique for generating an arbitrary digital data stream with very fine timing resolution. Note that this timing resolution specifies the output edge placement precision, not the bit rate. The resolution is determined by the difference between two propagation delays rather than by an absolute delay. Because this difference can be made very small, the circuit, called the delay vernier generator, can achieve unprecedented timing resolution in a particular circuit technology. Also, this very precise timing is obtained without requiring an extremely high speed clock. The generator architecture includes delay-locked loop calibration mechanisms to compensate for process and temperature variations. A prototype chip was fabricated in a 1.2-/spl mu/m CMOS technology, and measurements confirmed that resolutions as fine as 100 ps can be achieved reliably.}, number={4}, journal={IEEE JOURNAL OF SOLID-STATE CIRCUITS}, author={Moyer, GC and Clements, M and Liu, WT and Schaffer, T and Cavin, RK}, year={1997}, month={Apr}, pages={551–562} }
 @misc{hughes_gray_liu_cavin_1993, title={Method and apparatus for high speed digital sampling of a data signal}, volume={5,229,668}, number={1993 Jul. 20}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Hughes, T. A. and Gray, C. T. and Liu, W. and Cavin, R. K.}, year={1993} }