Ralph K. Cavin, III

Integrated circuit devices having on-chip adaptive bandwidth buses and related methods. (2006). Washington, DC: U.S. Patent and Trademark Office.

Bashirullah, R., Liu, W. T., Cavin, R., & Edwards, D. (2004). A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 12(8), 876–880. https://doi.org/10.1109/tvlsi.2004.831481

Bashirullah, R., Liu, W. T., & Cavin, R. K. (2003). Current-mode signaling in deep submicrometer global interconnects. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 11(3), 406–417. https://doi.org/10.1109/TVLSI.2003.812366

Kang, J. K., Liu, W. T., & Cavin, R. K. (1997). A CMOS high-speed data recovery circuit using the matched delay sampling technique. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 32(10), 1588–1596. https://doi.org/10.1109/4.634670

Moyer, G. C., Clements, M., Liu, W. T., Schaffer, T., & Cavin, R. K. (1997). The delay vernier pattern generation technique. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 32(4), 551–562. https://doi.org/10.1109/4.563677

Hughes, T. A., Gray, C. T., Liu, W., & Cavin, R. K. (1993). Method and apparatus for high speed digital sampling of a data signal. Washington, DC: U.S. Patent and Trademark Office.