@article{hari_ellington_floyd_2023, title={A Reflection-Mode N-Path Filter Tunable From 6 to 31 GHz}, volume={1}, ISSN={["1558-173X"]}, DOI={10.1109/JSSC.2023.3235976}, abstractNote={A 6-to-31-GHz reflection-mode $N$ -path filter is implemented in 45-nm SOI technology. The filter includes an on-chip hybrid coupler with through and coupled ports terminated with four-phase passive mixers. Each mixer provides a high impedance in-band and a matched, 50- $\Omega $ impedance out-of-band (OOB) that is provided by the ON-resistance of the switches. As such, in-band signals are reflected by the mixers, and OOB signals are absorbed. This enables reflection-mode bandpass filtering of the signal, with the center frequency set by the local-oscillator frequency. To increase selectivity, an active baseband (BB) load with adjustable bandwidth can be enabled to provide a second-order capacitive response, which increases the roll-off to 12 dB/octave. Measurements show that the filter can be tuned across 6–31 GHz with a maximum 3-dB RF bandwidth of 0.47 GHz for the passive BB and either 0.22 or 1.22 GHz for the active BB in narrowband or wideband modes. Filter insertion loss (IL) is < 7 dB in all three modes, whereas the noise figure exceeds IL by 1 dB at 6 GHz and 11 dB at 29 GHz in the active-wide mode. The filter provides a return loss of < 10 dB both in-band and OOB. In all three modes of the filter, the in-band input-referred third-order intercept point (IIP3) is<−2.2 dBm and the OOB IIP3 is > 11 dBm, whereas the maximum in-band input-referred P1 dB is −2 dBm. Clock circuitry consumes 75–320 mW from 6 to 31 GHz, whereas the active BBs consume 70 mW in the wideband mode and 90 mW in the narrowband mode.}, journal={IEEE JOURNAL OF SOLID-STATE CIRCUITS}, author={Hari, Sandeep and Ellington, Cody J. and Floyd, Brian A.}, year={2023}, month={Jan} }
 @article{ellington_hari_floyd_2023, title={Analysis and Design of Baseband Circuits for Higher-Order Reflection-Mode N-Path Filters}, volume={10}, ISSN={["1558-0806"]}, DOI={10.1109/TCSI.2023.3321872}, abstractNote={A design methodology for the synthesis of baseband circuits for higher-order reflection-mode N-path filters (RMNFs) is presented. Beginning with a linear time-invariant (LTI) model, equations are formulated that provide intuition for the designer with regard to signal and noise transfer through the RMNF. Building upon the mathematical foundation of the LTI model, an interdependence between signal and noise is explored and addressed. Furthermore, two baseband synthesis approaches are presented and connected with other state-of-the-art works. Finally, a 12-18GHz RMNF design with third-order selectivity (18dB/octave) is performed with analytical, simulated, and measured hardware results to validate the presented methodology.}, journal={IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS}, author={Ellington, Cody J. and Hari, Sandeep and Floyd, Brian A.}, year={2023}, month={Oct} }
 @article{dean_hari_floyd_2023, title={RF-to-Millimeter-Wave Receivers Employing Frequency-Translated Feedback}, volume={10}, ISSN={["1558-173X"]}, DOI={10.1109/JSSC.2023.3322136}, abstractNote={This article presents multi-band direct-conversion receivers (RXs) with frequency-translated negative feedback. The forward path includes a low-noise transconductance amplifier (LNTA) followed by four-phase passive mixers that drive baseband amplifiers. A feedback path employs tunable resistor banks attached to additional four-phase passive mixers, allowing tunable, frequency-selective input matching around a wide range of local oscillator (LO) frequencies. The passive mixers are driven by 25% duty-cycle, non-overlapping quadrature LO waveforms, and two different methods are presented for generating such waveforms. Two RX variants, differing in their LO generation schemes, are fabricated in 45-nm SOI CMOS. The first operates from 6 to 30 GHz, exhibiting greater than 25-dB gain and 4.1–10.5-dB noise figure (NF). A second operates from 10 to 50 GHz, achieving greater than 18-dB gain with 7.1–17-dB NF across the band. For either version, the instantaneous bandwidth is 960 MHz for the highest gain setting and 1375 MHz with reduced gain, measured at 10 GHz LO. The in-band third-order intercept point (IIP3) is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 5.4 dBm, the in-band IIP2 is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$+$</tex-math> </inline-formula> 16.5 dBm, and the out-of-band 1-dB blocker compression is greater than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 15 dBm. The RX core consumes 71 mW, while LO circuitry in each variant consumes 48–182 and 72–262 mW from 10 to 50 and 6 to 30 GHz, respectively.}, journal={IEEE JOURNAL OF SOLID-STATE CIRCUITS}, author={Dean, Jacob and Hari, Sandeep and Floyd, Brian A.}, year={2023}, month={Oct} }
 @article{dean_hari_bhat_floyd_2021, title={A 4-31GHz Direct-Conversion Receiver Employing Frequency-Translated Feedback}, ISSN={["1930-8833"]}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85118428066&partnerID=MN8TOARS}, DOI={10.1109/ESSCIRC53450.2021.9567779}, abstractNote={This paper presents a multi-band direct-conversion receiver with frequency-translated feedback. The forward path includes a low-noise transconductance amplifier followed by four-phase passive mixers which drive baseband amplifiers, and the feedback path employs tunable resistor banks attached to additional four-phase passive mixers, allowing tunable frequency-selective input matching. The receiver operates from 4–31 GHz exhibiting greater than 25 dB gain through 22 GHz and greater than 17 dB gain through 31 GHz. Noise figure is 5.2 to 9.8 dB, rising with frequency; input-referred 1-dB compression point is -17 dBm; and in-band IIP3 is -6.6 dBm. Out-of-band 1-dB blocker compression is greater than -12 dBm. The receiver core consumes 91 mW, whereas an integrated 2:1 frequency divider and pass-gate buffer for generating non-overlapping four-phase clocks consumes an additional 87–227 mW from 4–31 GHz, respectively.}, journal={ESSCIRC 2021 - IEEE 47TH EUROPEAN SOLID STATE CIRCUITS CONFERENCE (ESSCIRC)}, author={Dean, Jacob and Hari, Sandeep and Bhat, Avinash and Floyd, Brian A.}, year={2021}, pages={187–190} }
 @article{ren_hari_floyd_2020, title={A 20-33 GHz Direct-Conversion Transmitter in 45-nm SOI CMOS}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85104680228&partnerID=MN8TOARS}, DOI={10.1109/BCICTS48439.2020.9392967}, abstractNote={This paper presents a 20–33 GHz direct-conversion transmitter implemented in 45-nm RFSOI CMOS technology. The transmitter features a divider-based quadrature clock generation circuit, two current-combined double-balanced mixers, and a balanced power amplifier (PA) employing stacked FETs. The transmitter chip achieves 19.1 to 22.4 dB of conversion gain with saturated output power of 16.7 to 20.4 dBm over 20 to 33 GHz at the differential output. Image rejection and carrier suppression are more than 29 dB and 36 dB after calibration. At a carrier frequency of 28 GHz, the transmitter chip achieves an error vector magnitude (EVM) of 5.1 % with 12 Gbps using 64-QAM.}, journal={2020 IEEE BICMOS AND COMPOUND SEMICONDUCTOR INTEGRATED CIRCUITS AND TECHNOLOGY SYMPOSIUM (BCICTS)}, author={Ren, Tiantong and Hari, Sandeep and Floyd, Brian A.}, year={2020} }