@article{nigussie_schabel_lipa_mcilrath_patti_franzon_2022, title={Design Obfuscation Through 3-D Split Fabrication With Smart Partitioning}, volume={30}, ISSN={["1557-9999"]}, url={https://doi.org/10.1109/TVLSI.2022.3179304}, DOI={10.1109/TVLSI.2022.3179304}, abstractNote={We describe a design and fabrication experiment that has been performed to investigate a methodology for assessing the security of application specific integrated circuits (ASICs) fabricated in a split-manufacturing process based on 3-D integrated circuit (3DIC) technologies. The purpose of this process is to protect critical IP from reverse engineering if an adversary obtains either the fabricated wafers or their GDS. A number of 3DIC-based fabrication alternatives were evaluated, and one is selected for this experiment. Several designs, from the trivial to the complex, were used for the study. A self-test module was embedded in each design to facilitate the postfabrication testing. Various obfuscation techniques that include camouflage in the form of function and lookup table hiding and insertion of redundant logic in order to confuse potential attackers were applied. Smart partitioning was implemented for each design in an attempt to conceal vital functions. We introduced metrics that are based on the number of connection possibilities (<inline-formula> <tex-math notation="LaTeX">$C_{p}$ </tex-math></inline-formula>) and the depth of partitioning (<inline-formula> <tex-math notation="LaTeX">$P_{\mathrm{ depth}}$ </tex-math></inline-formula>) to measure the obfuscation strength. The results show that it should take more than 10 <sup>60</sup> years to reconstruct the netlist using a brute-force attack. Measurement results are presented showing fabrication success.}, number={9}, journal={IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Nigussie, Theodros and Schabel, Josh C. and Lipa, Steve and McIlrath, Lisa and Patti, Robert and Franzon, Paul}, year={2022}, month={Sep}, pages={1230–1243} }
 @article{nigussie_pan_lipa_pitts_delacruz_franzon_2021, title={Design Benefits of Hybrid Bonding for 3D Integration}, ISSN={["2377-5726"]}, DOI={10.1109/ECTC32696.2021.00296}, abstractNote={We present electrical and thermal analyses of 3D digital designs using hybrid bonding, specifically using the design rules, and other properties, for the XPERI DBI® technology at a $\mathrm{1.6}\ \mu \mathrm{m}$ pad pitch. We also go over the advantages of hybrid bonding over thermo-compression bonding (TCB) and 2D designs. Commercial 3D physical design tools were not mature when we did this work, so we came up with a methodology that builds on 2D tools. Our design flow includes scripts for optimal assignment of bonding locations, partitioning of netlist and delay constraints, and optimization techniques that involve iterating on delay constraints. Various partitioning schemes that include targeting long nets, managing flip-flop distribution between tiers, and minimum cut partitioning using an open source tool were analyzed. Because analysis results could vary from design to design, we propose potential metrics that can be used to identify designs that may benefit from 3DIC technology. Analysis results showed that we were able to reduce routed wire length by up to 57%. Logic power and total power decreased by up to 34% and 22% respectively. Silicon area also improved by 11%.11This work was supported, in part, by Xperi. DISTRIBUTION STATE-MENT A. Approved for public release: distribution unlimited.}, journal={IEEE 71ST ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2021)}, author={Nigussie, Theodros and Pan, Tse-Han and Lipa, Steve and Pitts, W. Shepherd and DeLaCruz, Javi and Franzon, Paul}, year={2021}, pages={1876–1881} }
 @article{franzon_davis_rotenberg_stevens_lipa_nigussie_pan_baker_schabel_dey_et al._2021, title={Design for 3D Stacked Circuits}, ISSN={["2380-9248"]}, DOI={10.1109/IEDM19574.2021.9720553}, abstractNote={2.5D and 3D technologies can give rise to a node equivalent of scaling due to improved connectivity. Aggressive exploitation scenarios include functional partitioning, circuit partitioning, logic on DRAM, design obfuscation and modular chiplets. Design issues that need to be addressed in pursuing such exploitations include thermal management, design for test and computer aided design.}, journal={2021 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)}, author={Franzon, P. and Davis, W. and Rotenberg, E. and Stevens, J. and Lipa, S. and Nigussie, T. and Pan, H. and Baker, L. and Schabel, J. and Dey, S. and et al.}, year={2021} }
 @inproceedings{srinivasan_chowdhury_forbes_widialaksono_zhang_schabel_ku_lipa_rotenberg_davis_et al._2017, title={H3 (heterogeneity in 3D): A logic-on-logic 3D-stacked heterogeneous multi-core processor}, DOI={10.1109/ICCD.2017.30}, abstractNote={A single-ISA heterogeneous multi-core processor(HMP) [2], [7] is comprised of multiple core types that all implement the same instruction-set architecture (ISA) but have different microarchitectures. Performance and energy is optimized by migrating a thread's execution among core types as its characteristics change. Simulation-based studies with two core types, one simple (low power) and the other complex (high performance), has shown that being able to switch cores as frequently as once every 1,000 instructions increases energy savings by 50% compared to switching cores once every 10,000 instructions, for the same target performance [10]. These promising results rely on extremely low latencies for thread migration. Here we present the H3 chip that uses 3D die stacking and novel microarchitecture to implement a heterogeneous multi-core processor (HMP) with low-latency fast thread migration capabilities. We discuss details of the H3 design and present power and performance results from running various benchmarks on the chip. The H3 prototype can reduce power consumption of benchmarks by up to 26%.}, booktitle={2017 IEEE International Conference on Computer Design (ICCD)}, author={Srinivasan, V. and Chowdhury, R. B. R. and Forbes, E. and Widialaksono, R. and Zhang, Z. Q. and Schabel, J. and Ku, S. and Lipa, S. and Rotenberg, E. and Davis, W. R. and et al.}, year={2017}, pages={145–152} }
 @inproceedings{franzon_priyadarshi_lipa_davis_thorolfsson_2013, title={Exploring early design tradeoffs in 3DIC}, DOI={10.1109/iscas.2013.6571901}, abstractNote={This The key to gaining substantial benefit from the use of 3DIC technology is to create 3D specific designs that do more than recast a 2D optimal design into the third dimension. This paper explores some of the approaches to creating 3D specific designs and the CAD tools that can help in that exploration. The power advantages of 3D design are illustrated in details. Results from different partitioning approaches (function, modular and circuit) are presented, together with early results from a thermal pathfinding tool.}, booktitle={2013 IEEE International Symposium on Circuits and Systems (ISCAS)}, author={Franzon, P. D. and Priyadarshi, S. and Lipa, S. and Davis, W. R. and Thorolfsson, T.}, year={2013}, pages={545–549} }
 @inproceedings{thorolfsson_lipa_franzon_2012, title={A 10.35 mW/GFlop Stacked SAR DSP unit using fine-grain partitioned 3D integration}, DOI={10.1109/cicc.2012.6330589}, abstractNote={In this paper we present a technique for implementing a fine-grain partitioned three-dimensional SAR DSP system using 3D placement of standard cells where only one of the 3D tiers is clocked to reduce clock power. We show how this technique was used to build the first fine-grain partitioned 3D integrated system to be demonstrated with silicon measurements in the literature, which is an ultra efficient floating-point synthetic aperture radar (SAR) DSP processing unit. The processing unit was fabricated in two tiers of GlobalFoundries, 1.5 V 130nm process that were 3D stacked face-to-face by Tezzaron. After fabrication the test chip was measured to consume 4.14 mW of power while running at 40 MHz operating for an operating efficiency of 10.35 mW/GFlop.}, booktitle={2012 ieee custom integrated circuits conference (cicc)}, author={Thorolfsson, T. and Lipa, S. and Franzon, Paul}, year={2012} }
 @article{shenderova_tyler_cunningham_ray_walsh_casulli_hens_mcguire_kuznetsov_lipa_2007, title={Nanodiamond and onion-like carbon polymer nanocomposites}, volume={16}, ISSN={["1879-0062"]}, DOI={10.1016/j.diamond.2006.11.086}, abstractNote={The current work demonstrates that nanodiamond (ND) of detonation origin and onion-like carbon (OLC) are valuable additives in multifunctional polymer composites, particularly for polymers used in microelectronic applications. We demonstrate that addition of ND to a polyimide matrix increases the thermal degradation temperature of the composites up to 30 °C and also improves adhesion. The addition of 2 wt.% of ND increases thermal conductivity of PDMS up to 15%. Finally, we also demonstrate that the addition of OLC to polydimethylsiloxane and polyurethane matrices increases the loss tangent of the composites.}, number={4-7}, journal={DIAMOND AND RELATED MATERIALS}, author={Shenderova, O. and Tyler, T. and Cunningham, G. and Ray, M. and Walsh, J. and Casulli, M. and Hens, S. and McGuire, G. and Kuznetsov, V. and Lipa, S.}, year={2007}, pages={1213–1217} }
 @article{shenderova_tyler_cunningham_ray_walsh_casulli_hens_mcguire_kuznetsov_lipa_2007, title={Nanodiamond and onion-like carbon polymer nanocomposites (vol 16, pg 1213, 2007)}, volume={16}, ISSN={["0925-9635"]}, DOI={10.1016/s0925-9635(07)00337-8}, number={9}, journal={DIAMOND AND RELATED MATERIALS}, author={Shenderova, O. and Tyler, T. and Cunningham, G. and Ray, M. and Walsh, J. and Casulli, M. and Hens, S. and McGuire, G. and Kuznetsov, V. and Lipa, S.}, year={2007}, month={Sep}, pages={1770–1770} }
 @article{wood_edwards_lipa_2001, title={Rotary traveling-wave oscillator arrays: A new clock technology}, volume={36}, ISSN={["1558-173X"]}, DOI={10.1109/4.962285}, abstractNote={Rotary traveling-wave oscillators (RTWOs) represent a new transmission-line approach to gigahertz-rate clock generation. Using the inherently stable LC characteristics of on-chip VLSI interconnect, the clock distribution network becomes a low-impedance distributed oscillator. The RTWO operates by creating a rotating traveling wave within a closed-loop differential transmission line. Distributed CMOS inverters serve as both transmission-line amplifiers and latches to power the oscillation and ensure rotational lock. Load capacitance is absorbed into the transmission-line constants whereby energy is recirculated giving an adiabatic quality. Unusually for an LC oscillator, multiphase (360/spl deg/) square waves are produced directly. RTWO structures are compact and can be wired together to form rotary oscillator arrays (ROAs) to distribute a phase-locked clock over a large chip. The principle is scalable to very high clock frequencies. Issues related to interconnect and field coupling dominate the design process for RTWOs. Taking precautions to avoid unwanted signal couplings, the rise and fall times of 20 ps, suggested by simulation, may be realized at low power consumption. Experimental results of the 0.25-/spl mu/m CMOS test chip with 950-MHz and 3.4-GHz rings are presented, indicating 5,5-ps jitter and 34-dB power supply rejection ratio (PSRR). Design errors in the test chip precluded meaningful rise and fall time measurements.}, number={11}, journal={IEEE JOURNAL OF SOLID-STATE CIRCUITS}, author={Wood, J and Edwards, TC and Lipa, S}, year={2001}, month={Nov}, pages={1654–1665} }