Samira Mirbagher Ajorpaz

Karuppanan, S., & Mirbagher Ajorpaz, S. (2023). An Attack on The Speculative Vectorization: Leakage from Higher Dimensional Speculation. https://doi.org/10.48550/ARXIV.2302.01131

Chacon, G., Garza, E., Jimborean, A., Ros, A., Gratz, P. V., Jimenez, D. A., & Mirbagher-Ajorpaz, S. (2022). Composite Instruction Prefetching. https://doi.org/10.1109/iccd56317.2022.00076

Testa, B., Mirbagher-Ajorpaz, S., & Jimenez, D. A. (2022). Dynamic Set Stealing to Improve Cache Performance. 2022 IEEE 34TH INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING (SBAC-PAD 2022), pp. 60–70. https://doi.org/10.1109/SBAC-PAD55451.2022.00017

Ajorpaz, S. M., Moghimi, D., Collins, J. N., Pokam, G., Abu-Ghazaleh, N., & Tullsen, D. (2022). EVAX: Towards a Practical, Pro-active & Adaptive Architecture for High Performance & Security. 2022 55TH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE (MICRO), pp. 1218–1236. https://doi.org/10.1109/MICRO56248.2022.00085

Mirbagher-Ajorpaz, S., Garza, E., Pokam, G., & Jimenez, D. A. (2020). CHiRP: Control-Flow History Reuse Prediction. Presented at the 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). https://doi.org/10.1109/micro50266.2020.00023

Mirbagher-Ajorpaz, S., Pokam, G., Mohammadian-Koruyeh, E., Garza, E., Abu-Ghazaleh, N., & Jimenez, D. A. (2020). PerSpectron: Detecting Invariant Footprints of Microarchitectural Attacks with Perceptron. Presented at the 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). https://doi.org/10.1109/micro50266.2020.00093

Garza, E., Mirbagher-Ajorpaz, S., Khan, T. A., & Jiménez, D. A. (2019). Bit-level perceptron prediction for indirect branches. Proceedings of the 46th International Symposium on Computer Architecture. Presented at the ISCA '19: The 46th Annual International Symposium on Computer Architecture, Phoenix, AZ. https://doi.org/10.1145/3307650.3322217

Mirbagher Ajorpaz, S., Garza, E., Jindal, S., & Jimenez, D. A. (2018). Exploring Predictive Replacement Policies for Instruction Cache and Branch Target Buffer. Presented at the 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA). https://doi.org/10.1109/isca.2018.00050