@article{nema_chunduru_kodigal_voskuilen_rodrigues_hemmert_feinberg_lee_awad_hughes_2023, title={ERAS: A Flexible and Scalable Framework for Seamless Integration of RTL Models with Structural Simulation Toolkit}, DOI={10.1109/IISWC59245.2023.00038}, abstractNote={The prevalence of custom Intellectual Properties (IPs) poses challenges for assessing their system-level performance and functional behavior. Register Transfer Level (RTL) simulation requires RTL-level integration with the rest of the system which is time- and resource-intensive. Similarly, developing functional and performance models of the IP requires considerable effort and expertise.This work proposes a framework, ERAS, that enables seamless integration of RTL IP models with high-level architectural simulators, such as Structural Simulation Toolkit (SST). The effectiveness of this framework is demonstrated through architectural exploration using a RISCV processor. Further, ERAS leverages SST’s multi-thread support to enhance simulation speed, effectively overcoming a key bottleneck of detailed RTL simulation. Evaluation with a dual-core RISCV-RTL configuration shows 1.83× simulation speed improvement compared to a serial simulation in gem5 as baseline.ERAS is now part of SST public repository: Link}, journal={2023 IEEE INTERNATIONAL SYMPOSIUM ON WORKLOAD CHARACTERIZATION, IISWC}, author={Nema, Shubham and Chunduru, Shiva Kaushik and Kodigal, Charan and Voskuilen, Gwendolyn and Rodrigues, Arun F. and Hemmert, Scott and Feinberg, Ben and Lee, Hyokeun and Awad, Amro and Hughes, Clayton}, year={2023}, pages={196–200} }
 @article{nema_kirschner_adak_agarwal_feinberg_rodrigues_marinella_awad_2022, title={Eris: Fault Injection and Tracking Framework for Reliability Analysis of Open-Source Hardware}, DOI={10.1109/ISPASS55109.2022.00027}, abstractNote={As transistors have been scaled over the past decade, modern systems have become increasingly susceptible to faults. Increased transistor densities and lower capacitances make a particle strike more likely to cause an upset. At the same time, complex computer systems are increasingly integrated into safety-critical systems such as autonomous vehicles. These two trends make the study of system reliability and fault tolerance essential for modern systems. To analyze and improve system reliability early in the design process, new tools are needed for RTL fault analysis.This paper proposes Eris, a novel framework to identify vulnerable components in hardware designs through fault-injection and fault propagation tracking. Eris builds on ESSENT—a fast C/C++ RTL simulation framework—to provide fault injection, fault tracking, and control-flow deviation detection capabilities for RTL designs. To demonstrate Eris’ capabilities, we analyze the reliability of the open source Rocket Chip SoC by randomly injecting faults during thousands of runs on four microbenchmarks. As part of this analysis we measure the sensitivity of different hardware structures to faults based on the likelihood of a random fault causing silent data corruption, unrecoverable data errors, program crashes, and program hangs. We detect control flow deviations and determine whether or not they are benign. Additionally, using Eris’ novel fault-tracking capabilities we are able to find 78% more vulnerable components in the same number of simulations compared to RTL-based fault injection techniques without these capabilities. We will release Eris as an open-source tool to aid future research into processor reliability and hardening.}, journal={2022 IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE (ISPASS 2022)}, author={Nema, Shubham and Kirschner, Justin and Adak, Debpratim and Agarwal, Sapan and Feinberg, Ben and Rodrigues, Arun F. and Marinella, Matthew J. and Awad, Amro}, year={2022}, pages={210–220} }