Shivam Priyadarshi

Works (8)

Updated: July 5th, 2023 15:46

2014 conference paper

Pathfinder3D: A framework for exploring early thermal tradeoffs in 3DIC

2014 IEEE International Conference on IC Design & Technology. Presented at the 2014 IEEE International Conference on IC Design & Technology (ICICDT).

By: S. Priyadarshi n, W. Davis n  & P. Franzon n 

topics (OpenAlex): 3D IC and TSV technologies; Additive Manufacturing and 3D Printing Technologies; VLSI and FPGA Design Techniques
TL;DR: A CAD flow and associated framework called Pathfinder3D is presented, which facilitates physically-aware system-level thermal simulation of 3DICs and facilitates early thermal evaluation of possible 3D design choices and thermal management techniques. (via Semantic Scholar)
Sources: NC State University Libraries, Crossref, NC State University Libraries
Added: August 6, 2018

2014 article

Thermal Pathfinding for 3-D ICs

Priyadarshi, S., Davis, W. R., Steer, M. B., & Franzon, P. D. (2014, May 21). IEEE Transactions on Components Packaging and Manufacturing Technology, Vol. 4, pp. 1159–1168.

By: S. Priyadarshi n, W. Davis n , M. Steer n & P. Franzon n 

author keywords: 3-D IC; electronic system-level (ESL); electrothermal simulation; pathfinding; through-silicon via (TSV); transaction-level simulation
topics (OpenAlex): 3D IC and TSV technologies; VLSI and FPGA Design Techniques; VLSI and Analog Circuit Testing
TL;DR: A pathfinding flow that integrates SystemC transaction-level electrical and dynamic thermal simulations to pass complex physical constraints to system architects in a convenient form is presented. (via Semantic Scholar)
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Sources: Web Of Science, NC State University Libraries
Added: August 6, 2018

2013 conference paper

Exploring early design tradeoffs in 3DIC

2013 IEEE International Symposium on Circuits and Systems (ISCAS), 545–549.

By: P. Franzon n , S. Priyadarshi n, S. Lipa n, W. Davis n  & T. Thorolfsson*

topics (OpenAlex): 3D IC and TSV technologies; Additive Manufacturing and 3D Printing Technologies; VLSI and FPGA Design Techniques
TL;DR: This paper explores some of the approaches to creating 3D specific designs and the CAD tools that can help in that exploration, together with early results from a thermal pathfinding tool. (via Semantic Scholar)
Sources: NC State University Libraries, NC State University Libraries
Added: August 6, 2018

2013 conference paper

Hetero(2) 3d integration: A scheme for optimizing efficiency/cost of chip multiprocessors

Proceedings of the fourteenth international symposium on quality electronic design (ISQED 2013), 1–7.

By: S. Priyadarshi n, N. Choudhary n, B. Dwiel n, A. Upreti n, E. Rotenberg n , R. Davis n , P. Franzon n 

topics (OpenAlex): 3D IC and TSV technologies; Parallel Computing and Optimization Techniques
TL;DR: This work proposes exploiting two complementary forms of heterogeneity to profitably exploit an immature technology for Chip Multiprocessors (CMP): 3D integration facilitates a technology alloy and application and microarchitectural heterogeneity is exploited to compensate for lower efficiency of old-technology cores. (via Semantic Scholar)
Sources: NC State University Libraries, NC State University Libraries
Added: August 6, 2018

2012 article

A Transient Electrothermal Analysis of Three-Dimensional Integrated Circuits

Harris, T. R., Priyadarshi, S., Melamed, S., Ortega, C., Manohar, R., Dooley, S. R., … al. (2012, January 12). IEEE Transactions on Components Packaging and Manufacturing Technology, p. 1.

By: T. Harris n, S. Priyadarshi n, S. Melamed n, C. Ortega*, R. Manohar *, S. Dooley*, N. Kriplani n, W. Davis n  ...

author keywords: 3DIC; electrothermal effects; thermal management; transient analysis
topics (OpenAlex): 3D IC and TSV technologies; Semiconductor materials and devices; Electromagnetic Compatibility and Noise Suppression
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Sources: Web Of Science, NC State University Libraries
Added: August 6, 2018

2012 article

Junction-Level Thermal Analysis of 3-D Integrated Circuits Using High Definition Power Blurring

Melamed, S., Thorolfsson, T., Harris, T. R., Priyadarshi, S., Franzon, P., Steer, M. B., & Davis, W. R. (2012, April 20). IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 31, pp. 676–689.

By: S. Melamed*, T. Thorolfsson*, T. Harris*, S. Priyadarshi n, P. Franzon n , M. Steer n, W. Davis n 

topics (OpenAlex): 3D IC and TSV technologies; Electronic Packaging and Soldering Technologies; Silicon Carbide Semiconductor Technologies
TL;DR: This paper presents a resistive mesh-based approach that improves on the fidelity of prior approaches by constructing a thermal model of the full structure of 3DICs, including the interconnect, and introduces a method for dividing the thermal response caused by a heat load into a high fidelity “near response” and a lower fidelity” in order to implement Power Blurring high definition (HD). (via Semantic Scholar)
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Sources: NC State University Libraries, NC State University Libraries
Added: August 6, 2018

2012 article

Parallel Transient Simulation of Multiphysics Circuits Using Delay-Based Partitioning

Priyadarshi, S., Saunders, C. S., Kriplani, N. M., Demircioglu, H., Davis, W. R., Franzon, P. D., & Steer, M. B. (2012, September 15). IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 31, pp. 1522–1535.

By: S. Priyadarshi n, C. Saunders*, N. Kriplani n, H. Demircioglu n, W. Davis n , P. Franzon n , M. Steer n

author keywords: Delay element; electrothermal simulation; multicore; multiphysics; parallel simulation; parallelization; transient simulation
topics (OpenAlex): Low-power high-performance VLSI design; Parallel Computing and Optimization Techniques; Real-time simulation and control systems
TL;DR: A parallel delay-based iterative approach for interfacing delay-partitioned subcircuits is applied, which achieves the reasonable accuracy of nonparallel circuit simulation if both incorporate the same interblock delay. (via Semantic Scholar)
Sources: Web Of Science, NC State University Libraries
Added: August 6, 2018

2011 article

SPICE-compatible physical model of nanocrystal floating gate devices for circuit simulation

Schinke, D., Priyadarshi, S., Pitts, W. S., Spigna, N. D., & Franzon, P. (2011, November 18). IET Circuits Devices & Systems, Vol. 5, pp. 477–483.

By: D. Schinke n, S. Priyadarshi n, W. Pitts n, N. Spigna n & P. Franzon n 

topics (OpenAlex): Semiconductor materials and devices; Advancements in Semiconductor Devices and Circuit Design; Quantum and electron transport phenomena
TL;DR: A comprehensive and accurate SPICE-compatible physical equation-based model of nanocrystal floating gate devices is developed based on uniform direct Tunnelling and Fowler-Nordheim tunnelling based on a Verilog-A module that captures the physical behaviours of programming and erasing the device. (via Semantic Scholar)
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Sources: Web Of Science, NC State University Libraries
Added: August 6, 2018

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