@article{lee_lichtenwalner_novak_misra_2011, title={Impact of AlTaO Dielectric Capping on Device Performance and Reliability for Advanced Metal Gate/High-k PMOS Application}, volume={58}, ISSN={["1557-9646"]}, DOI={10.1109/ted.2011.2160064}, abstractNote={We have investigated the effect of ultrathin Al-Ta-based capping layers on HfO2 and experimentally demonstrated that, with proper Al and Ta composition, an AlTaO capping layer is a good candidate dielectric for PMOSFET devices. Lower threshold voltage and significantly improved mobility were observed with AlTaO capping without degrading the dielectric properties. The addition of Ta in an AlTaO structure produces d-states in the Al2O3 matrix, resulting in an additional VT shift toward the PMOS band edge. This AlTaO capping layer not only modulates the device VT suitably for PMOS applications but also retards Al diffusion through the HfO2 layer, preventing Al-caused mobility degradation. Furthermore, the incorporation of a capping layer can improve reliability characteristics during the negative bias stress.}, number={9}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Lee, Bongmook and Lichtenwalner, Daniel J. and Novak, Steven R. and Misra, Veena}, year={2011}, month={Sep}, pages={2928–2935} } @article{lee_novak_lichtenwalner_yang_misra_2011, title={Investigation of the Origin of V-T/V-FB Modulation by La2O3 Capping Layer Approaches for NMOS Application: Role of La Diffusion, Effect of Host High-k Layer, and Interface Properties}, volume={58}, ISSN={["1557-9646"]}, DOI={10.1109/ted.2011.2159306}, abstractNote={The role of La₂O₃ capping in the VT/V_FB shift with various high- k and metal gate electrodes was systematically investigated. It was found that the La concentration at the high-k/SiO₂ interface is mainly responsible for the VT/V_FB modulation in NMOS devices, whereas the effect of the host high-k and gate electrodes on VT/V_FB is minimal. A 400-mV shift in VT from the control HfO₂ device with minimal degradation in mobility was obtained when a La₂O₃ layer was inserted between the high-k and SiO₂ layers. It was also found that the incorporation of La₂O₃ in the dielectric stack improves device reliability in terms of breakdown and positive-bias temperature instability characteristics. The main key for the V_FB shift is the ability of La diffusion through the host high-k material.}, number={9}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Lee, Bongmook and Novak, Steven R. and Lichtenwalner, Daniel J. and Yang, Xiangyu and Misra, Veena}, year={2011}, month={Sep}, pages={3106–3115} } @article{novak_lee_yang_misra_2010, title={Platinum Nanoparticles Grown by Atomic Layer Deposition for Charge Storage Memory Applications}, volume={157}, ISSN={["1945-7111"]}, DOI={10.1149/1.3365031}, abstractNote={This paper explores platinum nanoparticle formation during the early stages of growth by atomic layer deposition. Particle size and distribution can be controlled by altering growth parameters. The particles show excellent temperature stability up to 900°C as examined by transmission electron microscopy and in situ heating. Capacitance-voltage and charge retention measurements demonstrate the memory effect in metal-oxide-semiconductor capacitors with embedded nanoparticles. The size, density, charge storage, and temperature stability of the platinum nanoparticles make them attractive for use as charge storage layers for nonvolatile memory devices.}, number={6}, journal={JOURNAL OF THE ELECTROCHEMICAL SOCIETY}, author={Novak, Steven and Lee, Bongmook and Yang, Xiangyu and Misra, Veena}, year={2010}, pages={H589–H592} } @article{suresh_novak_wellenius_misra_muth_2009, title={Transparent indium gallium zinc oxide transistor based floating gate memory with platinum nanoparticles in the gate dielectric}, volume={94}, ISSN={["1077-3118"]}, DOI={10.1063/1.3106629}, abstractNote={A transparent memory device has been developed based on an indium gallium zinc oxide thin film transistor by incorporating platinum nanoparticles in the gate dielectric stack as the charge storage medium. The transfer characteristics of the device show a large clockwise hysteresis due to electron trapping and are attributed to the platinum nanoparticles. Effect of the gate bias stress (program voltage) magnitude, duration, and polarity on the memory window characteristics has been studied. Charge retention measurements were carried out and a loss of less than 25% of the trapped elec-trons was observed over 104 s indicating promising application as nonvolatile memory.}, number={12}, journal={APPLIED PHYSICS LETTERS}, author={Suresh, Arun and Novak, Steven and Wellenius, Patrick and Misra, Veena and Muth, John F.}, year={2009}, month={Mar} } @article{lee_biswas_novak_misra_2007, title={Characteristics of Ni/Gd FUSI for NMOS gate electrode applications}, volume={28}, ISSN={["1558-0563"]}, DOI={10.1109/LED.2007.897889}, abstractNote={This letter investigates the work function tuning of nickel/gadolinium (Ni/Gd) fully silicided (FUSI) gate electrodes on HfSiOx dielectrics. It was found that as the percentage of Gd in the Ni/Gd increased from 10% to 30%, the effective work function value after a one-step 450-degC FUSI anneal decreased from 4.75 to 4.35 eV. In addition, the presence of Gd also resulted in lowering of equivalent oxide thickness (EOT) values. The mechanism for a decreased EOT is attributed to the reduction of low-kappa interfacial layers by the presence of Gd in the gate stack. The decrease in work function is attributed to the creation of oxygen vacancies within the high-kappa layer created by the presence of Gd layer.}, number={7}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Lee, Bongmook and Biswas, Nivedita and Novak, Steven R. and Misra, Veena}, year={2007}, month={Jul}, pages={555–557} }