@article{chen_zhu_davis_franzon_2014, title={Adaptive and Reliable Clock Distribution Design for 3-D Integrated Circuits}, volume={4}, ISSN={["2156-3985"]}, DOI={10.1109/tcpmt.2014.2361356}, abstractNote={In this paper, we present novel techniques to handle the complexity and challenges in clock distribution for 3-D integrated circuit. First, we propose a novel active deskew technique to adaptively mitigate the cross-tier variations and the 3-D wiring asymmetry. The new deskew technique neither relies on an accurate through-silicon-vias model nor an accurate reference clock distribution. Second, we design a phase-mixer-based tunable-delay-buffer (TDB), which can be linearly tuned in 360° and tolerant to process-voltage-termperature (PVT) variations. Third, based on the new deskew technique and TDB design, we propose an efficient clock distribution network topology, which can be realized without a need of balanced H-tree. Moreover, a thermal profile-based optimization flow is developed to further improve the power efficiency and reduce design overhead. A case study shows that the proposed techniques are able to largely improve the clock skews. The optimization flow is capable of reducing the design cost to achieve a better tradeoff of the skew performance and the design overhead.}, number={11}, journal={IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY}, author={Chen, Xi and Zhu, Ting and Davis, William Rhett and Franzon, Paul D.}, year={2014}, month={Nov}, pages={1862–1870} }
 @article{zhu_yelten_steer_franzon_2013, title={Variation-Aware Circuit Macromodeling and Design Based on Surrogate Models}, volume={197}, ISBN={["978-3-642-34335-3"]}, ISSN={["2194-5365"]}, DOI={10.1007/978-3-642-34336-0_17}, abstractNote={This paper presents surrogate model-based methods to generate circuit performance models, device models, and high-speed IO buffer macromodels. Circuit performance models are built with design parameters and parametric variations, and they can be used for fast and systematic design space exploration and yield analysis. Surrogate models of the main device characteristics are generated in order to assess the effects of variability in analog circuits. A new variation-aware IO buffer macromodel is developed by integrating surrogate modeling and a physically-based model structure. The new IO model provides both good accuracy and scalability for signal integrity analysis.}, journal={SIMULATION AND MODELING METHODOLOGIES, TECHNOLOGIES AND APPLICATIONS}, author={Zhu, Ting and Yelten, Mustafa Berke and Steer, Michael B. and Franzon, Paul D.}, year={2013}, pages={255–269} }
 @article{zhu_steer_franzon_2012, title={Surrogate Model-Based Self-Calibrated Design for Process and Temperature Compensation in Analog/RF Circuits}, volume={29}, ISSN={0740-7475}, DOI={10.1109/mdt.2012.2220332}, abstractNote={Analog circuits designed in submicrometer nodes suffer from process variations, typically requiring calibration in order to center their performance parameters and to recover yield loss. This article presents a design flow to find appropriate tuning knob settings to compensate for different process variation scenarios.}, number={6}, journal={IEEE Design Test of Computers}, author={Zhu, T. and Steer, M. B. and Franzon, P. D.}, year={2012}, month={Dec}, pages={74–83} }
 @article{zhu_steer_franzon_2011, title={Accurate and Scalable IO Buffer Macromodel Based on Surrogate Modeling}, volume={1}, ISSN={["2156-3985"]}, DOI={10.1109/tcpmt.2011.2138704}, abstractNote={In this paper, a new method is proposed to generate accurate and scalable macromodels for input/output buffers. The method characterizes the physically based model elements with adaptive multivariate surrogate modeling techniques in order to achieve high fidelity and process–voltage–temperature scalability. Both single-ended and differential output buffer circuit examples demonstrate that the proposed modeling method offers good accuracy and flexible scalability to facilitate signal integrity analysis.}, number={8}, journal={IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY}, author={Zhu, Ting and Steer, Michael B. and Franzon, Paul D.}, year={2011}, month={Aug}, pages={1240–1249} }
 @article{chen_zhu_davis_2011, title={Three-dimensional SRAM design with on-chip access time measurement}, volume={47}, ISSN={["1350-911X"]}, DOI={10.1049/el.2010.3701}, abstractNote={An SRAM design in a 3D 0.18 µm silicon-on-insulator technology is presented. A novel delay-locked loop based access time measurement circuit was designed on-chip for accurately evaluating the 3D SRAM performance. Results show that a 32% improvement in the access time is gained by using 3D technology.}, number={8}, journal={ELECTRONICS LETTERS}, author={Chen, X. and Zhu, T. and Davis, W. R.}, year={2011}, month={Apr}, pages={485–486} }
 @inproceedings{zhu_franzon_2009, title={An enhanced macromodeling approach for differential output drivers}, DOI={10.1109/bmas.2009.5338889}, abstractNote={This paper presents an approach for building new compact macromodels of differential output drivers. Composed of enhanced physical-based elements, the new models are capable of capturing the important intrinsic nonlinear and dynamic characteristics of the drivers. We demonstrate the approach with two typical digital drivers, low-voltage differential signaling (LVDS) driver and pre-emphasis driver. The obtained macromodels achieve excellent accuracy in capturing behaviors at various input patterns, loading conditions and supply voltages.}, booktitle={BMAS 2009: Proceedings of the 2009 IEEE International Behavioral Modeling and Simulation Workshop}, author={Zhu, T. and Franzon, Paul}, year={2009}, pages={54–59} }
 @inproceedings{zhu_franzon_2009, title={Application of surrogate modeling to generate compact and PVT-sensitive IBIS models}, DOI={10.1109/epeps.2009.5338472}, abstractNote={A new proposal of applying surrogate-modeling in Input-output Buffer Information Specification (IBIS) is presented. It saves the IBIS data storage resource, extends the model utility to various process-voltage-temperature (PVT) simulations and eliminates the data interpolation deviations.}, booktitle={Electrical Performance of Electronic Packaging and Systems}, author={Zhu, T. and Franzon, Paul}, year={2009}, pages={77–80} }