Works (2)
Updated: July 5th, 2023 15:41
2014 article
Adaptive and Reliable Clock Distribution Design for 3-D Integrated Circuits
Chen, X., Zhu, T., Davis, W. R., & Franzon, P. (2014, October 20). IEEE Transactions on Components Packaging and Manufacturing Technology, Vol. 4, pp. 1862–1870.
author keywords: 3-D integrated circuit (3-D IC); adaptive; clock distribution; deskew; optimization; process-voltage-temperature (PVT) variation; stacking; thermal profile; through-silicon-via (TSV); tunable-delay-buffer (TDB)
topics (OpenAlex): 3D IC and TSV technologies; VLSI and Analog Circuit Testing; Interconnection Networks and Systems
TL;DR:
A novel active deskew technique to adaptively mitigate the cross-tier variations and the 3-D wiring asymmetry is proposed and a thermal profile-based optimization flow is developed to further improve the power efficiency and reduce design overhead.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy
(OpenAlex)
9. Industry, Innovation and Infrastructure
(Web of Science)
Sources: Web Of Science, NC State University Libraries
Added: August 6, 2018
2011 conference paper
Adaptive clock distribution for 3D integrated circuits
2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, 91–94.
topics (OpenAlex): 3D IC and TSV technologies; Interconnection Networks and Systems; VLSI and FPGA Design Techniques
TL;DR:
A robust tunable-delay-buffer circuit and a novel active de-skew method are developed in order to handle the cross-die variations, thermal gradients, and wiring asymmetry in 3D ICs.
(via Semantic Scholar)
Sources: NC State University Libraries, NC State University Libraries
Added: August 6, 2018