The prevalence of custom Intellectual Properties (IPs) poses challenges for assessing their system-level performance and functional behavior. Register Transfer Level (RTL) simulation requires RTL-level integration with the rest of the system which is time- and resource-intensive. Similarly, developing functional and performance models of the IP requires considerable effort and expertise.This work proposes a framework, ERAS, that enables seamless integration of RTL IP models with high-level architectural simulators, such as Structural Simulation Toolkit (SST). The effectiveness of this framework is demonstrated through architectural exploration using a RISCV processor. Further, ERAS leverages SST’s multi-thread support to enhance simulation speed, effectively overcoming a key bottleneck of detailed RTL simulation. Evaluation with a dual-core RISCV-RTL configuration shows 1.83× simulation speed improvement compared to a serial simulation in gem5 as baseline.ERAS is now part of SST public repository: Link