2024 journal article
Mitigating Voltage Imbalance Across Series-Connected 10 kV SiC JBS Diodes in a Medium-Voltage High-Power 3L-NPC Converter
IEEE TRANSACTIONS ON POWER ELECTRONICS, 39(3), 2896–2911.
This article presents a design methodology for <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> snubbers to address dynamic voltage imbalance in series-connected 10 kV SiC junction barrier Schottky (JBS) diodes, utilized in a 3-level (3L) neutral point clamped (NPC) converter. The proposed method considers the effect of bus bar inductance, unequal diode junction capacitance, baseplate capacitance, and common mode (CM) choke tied between the heat sink and midpoint of the dc link capacitor on snubber losses and turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> voltage mismatch across series-connected diodes. In addition, the effect of hard-switched turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> across complementary SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s has been considered on snubber loss and dynamic voltage balancing across SiC JBS diodes. The following steps have been used to simplify the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> snubber design: modeling the switching transition across series-connected 10 kV SiC JBS diodes and 10 kV SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s on two-level clamped inductive switching test setup, modification of snubber capacitor and switching transition model for 3L-NPC topology, using the experimental data, and modification of snubber resistor using experimental data from 3L-NPC setup with CM choke. Key design parameters obtained from the proposed model have been compared with the experimentally obtained data, which validates the accuracy of the model. Experimental results at the 7 kV dc bus show that the designed <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> snubber constrains the turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> voltage mismatch, snubber loss, and turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> transition time within the specified limit.