The power, performance, and area (PPA) of a System-on-Chip (SoC) is known only after a months-long process. This process includes iterations over the architectural design, register transfer level implementation, RTL synthesis, and place and route. Knowing the PPA estimates for a system early in the design stages can help resolve tradeoffs that will affect the final design. This work presents a machine learning approach using gradient boost models and neural networks to fast and accurately predict the PPA. This work focuses on reducing the number of samples used to create the models. The models use transfer learning to predict the PPA for new design configurations and corner conditions based on previous models. The models predict the PPA as a function of parameters accessible during the RTL synthesis. The proposed models achieved PPA predictions up to 99% accurate and using as few as 10 data samples can achieve accuracies better than 96%.