A systolic array architecture is proposed for an inverse QR algorithm for recursive least squares signal processing. This algorithm provides a solution for the least squares filter vector which does not require the computationally intensive step of backsubstitution needed in the direct QR method. The inverse QR algorithm is therefore highly amenable to a parallel implementation, resulting in a structure which produces the N filter coefficients every N + 1 clock cycles. Within the paper, the individual processing elements contained in the inverse QR algorithm are outlined, after which it is demonstrated how these processing elements may be connected to implement the overall inverse QR array. Timing considerations, data rates, latency and throughput are also discussed.