2018 conference paper
Estimation and minimization of power loop inductance in 135 kW SiC traction inverter
Thirty-third annual ieee applied power electronics conference and exposition (apec 2018), 1772–1777.
The paper discusses the estimation and minimization of commutation loop inductance for a printed circuit board (PCB) busbar based 135 kW SiC inverter with a 1 kV DC link using finite element analysis (FEA) simulations. For the inductance estimation of the power module (Wolfspeed: HT-3231-R), PCB busbar, and customized interconnects constituting the commutation loop have been modelled accurately in Ansys Q3D Extractor. Based on the simulation results, subsequent modification to the original PCB busbar design has been proposed to lower the loop inductance. FEA simulation results have resulted in an optimized PCB busbar with lower commutation loop inductance, thereby limiting the device voltage spike well below its rated value. Loop inductance results from the Q3D simulation have been validated through double pulse tests (DPT) and the performance improvements achieved therefore have been highlighted.