Works (4)

Updated: July 5th, 2023 16:04

2000 journal article

Properties of rescheduling size invariance for dynamic rescheduling-based VLIW cross-generation compatibility

IEEE TRANSACTIONS ON COMPUTERS, 49(8), 814โ€“825.

By: T. Conte n & S. Sathaye*

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
author keywords: microarchitecture; processor architecture; instruction cache; VLIW; instruction-set encoding; list encoding
Source: Web Of Science
Added: August 6, 2018

2000 journal article

System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 8(2), 129โ€“137.

By: T. Conte n, K. Menezes*, S. Sathaye* & M. Toburen n

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
author keywords: high-level synthesis; instruction-level parallelism; near-optimal search; power dissipation; superscalar
Source: Web Of Science
Added: August 6, 2018

1998 journal article

MPS: Miss-path scheduling for multiple-issue processors

IEEE TRANSACTIONS ON COMPUTERS, 47(12), 1382โ€“1397.

By: S. Banerjia*, S. Sathaye*, K. Menezes* & T. Conte n

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
author keywords: multiple instruction issue; miss path scheduling; instruction level parallelism; schedule cache
Source: Web Of Science
Added: August 6, 2018

1997 article

Optimization of VLIW compatibility systems employing dynamic rescheduling

Conte, T. M., & Sathaye, S. W. (1997, April). INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING, Vol. 25, pp. 83โ€“112.

By: T. Conte n & S. Sathaye n

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
author keywords: object-code compatibility; dynamic rescheduling; instruction level parallelism
Source: Web Of Science
Added: August 6, 2018