Sumedh W. Sathaye

Properties of rescheduling size invariance for dynamic rescheduling-based VLIW cross-generation compatibility

IEEE Transactions on Computers, 49(8), 814–825.

System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 8(2), 129–137.

MPS: Miss-path scheduling for multiple-issue processors

IEEE Transactions on Computers, 47(12), 1382–1397.

Optimization of VLIW compatibility systems employing dynamic rescheduling

International Journal of Parallel Programming, 25(2), 83–112.