Sumedh W. Sathaye

Works (4)

Updated: July 5th, 2023 16:04

2000 journal article

Properties of rescheduling size invariance for dynamic rescheduling-based VLIW cross-generation compatibility

IEEE TRANSACTIONS ON COMPUTERS, 49(8), 814–825.

By: T. Conte n & S. Sathaye*

author keywords: microarchitecture; processor architecture; instruction cache; VLIW; instruction-set encoding; list encoding
TL;DR: This paper shows that the changes in the page size are only due to insertion and/or deletion of NOPs in the code, and presents an ISA encoding, called list encoding, which does not require explicit encoding of the NOPa of the code. (via Semantic Scholar)
Source: Web Of Science
Added: August 6, 2018

2000 journal article

System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 8(2), 129–137.

By: T. Conte n, K. Menezes*, S. Sathaye* & M. Toburen n

author keywords: high-level synthesis; instruction-level parallelism; near-optimal search; power dissipation; superscalar
TL;DR: This paper presents systematic techniques to find low-power high-performance superscalar processors tailored to specific user applications and the use of a near-optimal search to tailor a processor design to a benchmark. (via Semantic Scholar)
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Source: Web Of Science
Added: August 6, 2018

1998 journal article

MPS: Miss-path scheduling for multiple-issue processors

IEEE TRANSACTIONS ON COMPUTERS, 47(12), 1382–1397.

By: S. Banerjia*, S. Sathaye*, K. Menezes* & T. Conte n

author keywords: multiple instruction issue; miss path scheduling; instruction level parallelism; schedule cache
TL;DR: This paper presents the design of a multiple issue processor that uses an alternative approach called miss path scheduling or MPS, which is removed from the processor pipeline altogether and placed on the path between the instruction cache and the next level of memory. (via Semantic Scholar)
Source: Web Of Science
Added: August 6, 2018

1997 article

Optimization of VLIW compatibility systems employing dynamic rescheduling

Conte, T. M., & Sathaye, S. W. (1997, April). INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING, Vol. 25, pp. 83–112.

By: T. Conte n & S. Sathaye n

author keywords: object-code compatibility; dynamic rescheduling; instruction level parallelism
TL;DR: This paper presents a technique called Dynamic Rescheduling that applies software techniques dynamically, using intervention by the OS: at each first-time page fault, the page of code is rescheduled for the new generation, if required. (via Semantic Scholar)
Source: Web Of Science
Added: August 6, 2018

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