@article{conte_sathaye_2000, title={Properties of rescheduling size invariance for dynamic rescheduling-based VLIW cross-generation compatibility}, volume={49}, ISSN={["0018-9340"]}, DOI={10.1109/12.868027}, abstractNote={The object-code compatibility problem in VLIW architectures stems from their statically scheduled nature. Dynamic rescheduling (DR) is a technique to solve the compatibility problem in VLIWs. DR reschedules program code pages at first-time page faults, i.e., when the code pages are accessed for the first time during execution. Treating a page of code as the unit of rescheduling makes it susceptible to the hazards of changes in the page size during the process of rescheduling. This paper shows that the changes in the page size are only due to insertion and/or deletion of NOPs in the code. Further, it presents an ISA encoding, called list encoding, which does not require explicit encoding of the NOPs in the code. Algorithms to perform rescheduling on acyclic code and cyclic code are presented, followed by the discussion of the property of rescheduling-size invariance (RSI) satisfied by list encoding.}, number={8}, journal={IEEE TRANSACTIONS ON COMPUTERS}, author={Conte, TM and Sathaye, S}, year={2000}, month={Aug}, pages={814–825} }
 @article{conte_menezes_sathaye_toburen_2000, title={System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design}, volume={8}, ISSN={["1063-8210"]}, DOI={10.1109/92.831433}, abstractNote={This paper presents systematic techniques to find low-power high-performance superscalar processors tailored to specific user applications. The model of power is novel because it separates power into architectural and technology components. The architectural component is found via trace-driven simulation, which also produces performance estimates. An example technology model is presented that estimates the technology component, along with critical delay time and real estate usage. This model is based on case studies of actual designs. It is used to solve an important problem: decreasing power consumption in a superscalar processor without greatly impacting performance. Results are presented from runs using simulated annealing to reduce power consumption subject to performance reduction bounds. The major contributions of this paper are the separation of architectural and technology components of dynamic power the use of trace-driven simulation for architectural power measurement, and the use of a near-optimal search to tailor a processor design to a benchmark.}, number={2}, journal={IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS}, author={Conte, TM and Menezes, KN and Sathaye, SW and Toburen, MC}, year={2000}, month={Apr}, pages={129–137} }
 @article{banerjia_sathaye_menezes_conte_1998, title={MPS: Miss-path scheduling for multiple-issue processors}, volume={47}, ISSN={["1557-9956"]}, DOI={10.1109/12.737684}, abstractNote={Many contemporary multiple issue processors employ out-of-order scheduling hardware in the processor pipeline. Such scheduling hardware can yield good performance without relying on compile-time scheduling. The hardware can also schedule around unexpected run-time occurrences such as cache misses. As issue widths increase, however, the complexity of such scheduling hardware increases considerably and can have an impact on the cycle time of the processor. This paper presents the design of a multiple issue processor that uses an alternative approach called miss path scheduling or MPS. Scheduling hardware is removed from the processor pipeline altogether and placed on the path between the instruction cache and the next level of memory. Scheduling is performed at cache miss time as instructions are received from memory. Scheduled blocks of instructions are issued to an aggressively clocked in-order execution core. Details of a hardware scheduler that can perform speculation are outlined and shown to be feasible. Performance results from simulations are presented that highlight the effectiveness of an MPS design.}, number={12}, journal={IEEE TRANSACTIONS ON COMPUTERS}, author={Banerjia, S and Sathaye, SW and Menezes, KN and Conte, TM}, year={1998}, month={Dec}, pages={1382–1397} }
 @article{conte_sathaye_1997, title={Optimization of VLIW compatibility systems employing dynamic rescheduling}, volume={25}, ISSN={["1573-7640"]}, DOI={10.1007/BF02700048}, number={2}, journal={INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING}, author={Conte, TM and Sathaye, SW}, year={1997}, month={Apr}, pages={83–112} }