@article{schaffer_glaser_franzon_2004, title={Chip-package co-implementation of a triple DES processor}, volume={27}, ISSN={["1521-3323"]}, DOI={10.1109/TADVP.2004.824944}, abstractNote={This paper describes the design and implementation of a dedicated data encryption standard (DES) processor. The processor consists of three 0.6 /spl mu/m complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) mounted on a single MCM-D thin-film substrate. Each chip can operate on an individual data stream, or the three can be cascaded to implement the so-called "triple-DES" (3DES) function for increased security. Measurements show 3DES operation at 110 MHz, which translates to a throughput of over 7 Gb/s, the highest reported 3DES throughput to date. System features which contribute to this throughput are the use of area-array (flip-chip) input/output (I/O) and global IC power/ground/clock distribution in the MCM package. In this case, package-level distribution reduced clock skew by 150 ps, and reduced the chip area required for power distribution by 20%. This paper also includes measurements of switching noise of the MCM's V/sub dd/ plane and how it correlates with a simple model of the system power distribution.}, number={1}, journal={IEEE TRANSACTIONS ON ADVANCED PACKAGING}, author={Schaffer, T and Glaser, A and Franzon, PD}, year={2004}, month={Feb}, pages={194–202} }
 @article{moyer_clements_liu_schaffer_cavin_1997, title={The delay vernier pattern generation technique}, volume={32}, ISSN={["0018-9200"]}, DOI={10.1109/4.563677}, abstractNote={The authors describe a new technique for generating an arbitrary digital data stream with very fine timing resolution. Note that this timing resolution specifies the output edge placement precision, not the bit rate. The resolution is determined by the difference between two propagation delays rather than by an absolute delay. Because this difference can be made very small, the circuit, called the delay vernier generator, can achieve unprecedented timing resolution in a particular circuit technology. Also, this very precise timing is obtained without requiring an extremely high speed clock. The generator architecture includes delay-locked loop calibration mechanisms to compensate for process and temperature variations. A prototype chip was fabricated in a 1.2-/spl mu/m CMOS technology, and measurements confirmed that resolutions as fine as 100 ps can be achieved reliably.}, number={4}, journal={IEEE JOURNAL OF SOLID-STATE CIRCUITS}, author={Moyer, GC and Clements, M and Liu, WT and Schaffer, T and Cavin, RK}, year={1997}, month={Apr}, pages={551–562} }