@article{osburn_de_yee_srivastava_2000, title={Design and integration considerations for end-of-the roadmap ultrashallow junctions}, volume={18}, ISSN={["1071-1023"]}, DOI={10.1116/1.591195}, abstractNote={Device simulations and response surface analysis have been used to quantify the trade-offs and issues encountered in designing ultrashallow junctions for the 250–50 nm generations of complimentary metal-oxide-semiconductor ultralarge scale integration technology. The design of contacting and extension junctions is performed to optimize short channel effects, performance, and reliability, while meeting the National Technology Roadmap for Semiconductors off-state leakage specifications. A maxima in saturated drive current is observed for an intermediate extension junction depth (∼20 nm for 100 nm technology): shallower junctions lead to higher series resistance, and deeper junctions result in more severe short channel effects. The gate-to-junction overlap required to preserve drive current was seen to depend on junction abruptness. For a perfectly abrupt junction, it is not necessary for the gate to overlap the junction. Performance depends on many parameters, including: overlap of gate to extension junction, junction capacitance, and parasitic series resistance, which depends on the doping gradient at the junction (spreading resistance), the extension series resistance, and the contact resistance. Extraction of these parameters using I–V or C–V measurements can potentially lead to erroneous conclusions about lateral junction excursion and abruptness.}, number={1}, journal={JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B}, author={Osburn, CM and De, I and Yee, KF and Srivastava, A}, year={2000}, pages={338–345} }
 @article{de_johri_srivastava_osburn_2000, title={Impact of gate workfunction on device performance at the 50 nm technology node}, volume={44}, ISSN={["0038-1101"]}, DOI={10.1016/S0038-1101(99)00323-8}, abstractNote={The optimal gate electrode workfunction was determined for the 50 nm technology node using a simulation strategy that takes into account the impact of short-channel effects on device performance in uniformly doped and super-steep-retrograde doped channels in conventional and dynamic threshold operation. Classical device simulations suggest that the optimal workfunction is such that the gate Fermi level is 0.2 eV below (above) the conduction (valence) band edge of silicon for NMOS (PMOS) devices. However, when quantum mechanical effects are taken into account, the optimal workfunction is such that the gate Fermi level coincides with the conduction (valence) band edge. Midgap gates are not viable because the resulting short-channel effects are too severe. In a surrounding-gate transistor the optimal workfunction is attained when the gate Fermi level is 0.35 eV below (above) the conduction (valence) band edge in NMOS (PMOS) device. Midgap gates are not viable because the resulting threshold voltage is too high and cannot be reduced by lowering the substrate doping.}, number={6}, journal={SOLID-STATE ELECTRONICS}, author={De, I and Johri, D and Srivastava, A and Osburn, CM}, year={2000}, month={Jun}, pages={1077–1080} }
 @article{srivastava_1999, title={Influence of BJT transit frequency limit relation to MOSFET parameters on the switching speed of BiCMOS digital circuits}, volume={9}, number={2}, journal={VLSI Design (Yverdon, Switzerland)}, author={Srivastava, A.}, year={1999}, pages={203–211} }
 @article{srivastava_heinisch_vogel_parker_osburn_masnari_wortman_hauser_1998, title={Evaluation of 2.0 nm grown and deposited dielectrics in 0.1 mu m PMOSFETs}, volume={525}, ISBN={["1-55899-431-9"]}, ISSN={["0272-9172"]}, DOI={10.1557/proc-525-163}, abstractNote={ABSTRACT}, journal={RAPID THERMAL AND INTEGRATED PROCESSING VII}, author={Srivastava, A and Heinisch, HH and Vogel, E and Parker, C and Osburn, CM and Masnari, NA and Wortman, JJ and Hauser, JR}, year={1998}, pages={163–170} }
 @article{sun_bartholomew_bellur_srivastava_osburn_masnari_westhoff_1998, title={Parasitic resistance considerations of using elevated source/drain technology for deep submicron metal oxide semiconductor field effect transistors}, volume={145}, ISSN={["1945-7111"]}, DOI={10.1149/1.1838607}, abstractNote={Device drive current, parasitic resistance, and junction leakage current have been studied using silicided and non-silicided deep submicron elevated source/drain (ESD) n-channel metal oxide semiconductor field effect transistors (NMOSFETs). This study illustrated the effects of doping profile in the elevated S/D region, junction depth in the substrate, and doping level in the source/drain extension. Compared to devices having nonelevated junctions with the same substrate doping profile, MOSFETs with a profile-doped elevated S/D, used to contact an ultrashallow junction formed before selective epitaxial growth, had higher drive currents and demonstrated the ability of the elevated junction to reduce the extrinsic resistance. Measurements of drive currents in ESD devices showed that (i) the lightly doped region at the bottom of a profile-doped elevated layer introduces additional extrinsic resistance, and (ii) the locally deeper junction beneath the epi facets extends laterally toward the channel and shortens the drain extension length, thereby reducing the intrinsic resistance. Silicided devices had higher drive current and reduced parasitic resistance when the silicide/silicon interfacial dopant concentrations remained high (>1 x 10 20 /cm 3 ) after silicidation. The lowest total parasitic resistance was achieved when the elevated S/D was used to give a small contact resistance to a shallow junction and a moderately doped drain extension was used to lower the resistance of the source/drain extension tab.}, number={6}, journal={JOURNAL OF THE ELECTROCHEMICAL SOCIETY}, author={Sun, J and Bartholomew, RF and Bellur, K and Srivastava, A and Osburn, CM and Masnari, NA and Westhoff, R}, year={1998}, month={Jun}, pages={2131–2137} }
 @article{daubert_steffe_srivastava_1998, title={Predicting the electrorheological behavior of milk chocolate}, volume={21}, DOI={10.1111/j.1745-4530.1998.tb00450.x}, abstractNote={ABSTRACT}, number={3}, journal={Journal of Food Process Engineering}, author={Daubert, C. R. and Steffe, J. F. and Srivastava, A. K.}, year={1998}, pages={249–261} }
 @inproceedings{srivastava_sun_bellur_bartholomew_o'neil_celik_osburn_masnari_ozturk_westhoff_et al._1997, title={A 0.18 ?m CMOS technology for elevated source/drain MOSFETs using selective silicon epitaxy}, booktitle={ULSI science and technology/1997: Proceedings of the Sixth International Symposium on UltraLarge Scale Integration Science and Technology (Proceedings (Electrochemical Society); v. 97-3)}, publisher={Pennington, NJ: Electrochemical Society}, author={Srivastava, A. and Sun, J. and Bellur, K. and Bartholomew, R. F. and O'Neil, P. and Celik, S. M. and Osburn, C. M. and Masnari, N. A. and Ozturk, M. C. and Westhoff, R. and et al.}, year={1997}, pages={571–585} }
 @article{sun_bartholomew_bellur_srivastava_osburn_masnari_westhoff_1997, title={A comparative study of n(+)/p junction formation for deep submicron elevated source/drain metal oxide semiconductor field effect transistors}, volume={144}, ISSN={["1945-7111"]}, DOI={10.1149/1.1838066}, abstractNote={Ultrashallow elevated n'/p junctions (∼75 nm) incorporating selectively deposited epitaxial silicon layers were fabricated. The undoped epi layers (∼100 nm) were deposited on exposed diffusion areas in an Advanced Semiconductor Material Epsilon I system specifically designed for low thermal budget single-wafer processing. Shallow junctions (∼75 nm) were formed by ion implantation (As, 4 x 10 15 /cm 2 , 80 keV) into undoped epi layers and out-diffusion into the underlying substrate. Alternatively, an ion implanted (As, 4 x 10 15 /cm 2 , 60 keV) elevated layer was utilized to contact a shallow junction, which was formed (As, 1.5 x 10 15 /cm 2 , 15 keV) before the epi deposition. All junctions were annealed at 950°C for 10 s. Nonsilicided elevated junctions and conventional nonelevated (As, 1.5 x 10 15 /cm 2 , 15 keV) ones displayed very similar junction characteristics. Silicided nonelevated ultrashallow junctions, however, showed large reverse leakage current due to the substrate consumption. Both silicided elevated (post-epi and pre-epi) junctions exhibited excellent forward characteristics and low reverse leakage current. The difference in the reverse leakage characteristics of these two elevated junctions was attributed to the epi faceting formed at the sidewall edge of localized oxidation of silicon isolation. Deep submicron n = channel metal oxide semiconductor field effect transistors incorporating these junctions were also fabricated and electrically tested. Both elevated source/drain (S/D) devices show superior current driving capability compared to nonelevated ones as a result of much reduced parasitic resistance from contact source/drain junctions.}, number={10}, journal={JOURNAL OF THE ELECTROCHEMICAL SOCIETY}, author={Sun, J and Bartholomew, RF and Bellur, K and Srivastava, A and Osburn, CM and Masnari, NA and Westhoff, R}, year={1997}, month={Oct}, pages={3659–3664} }
 @inproceedings{sun_bartholomew_bellur_srivastava_osburn_masnari_westhoff_1997, title={Parasitic resistance considerations of using elevated source/drain for deep submicron MOSFET technology}, booktitle={ULSI science and technology/1997: Proceedings of the Sixth International Symposium on UltraLarge Scale Integration Science and Technology (Proceedings (Electrochemical Society); v. 97-3)}, publisher={Pennington, NJ: Electrochemical Society}, author={Sun, J. and Bartholomew, R. F. and Bellur, K. and Srivastava, A. and Osburn, C. M. and Masnari, N. A. and Westhoff, R.}, year={1997}, pages={587–597} }
 @article{sun_bartholomew_bellur_srivastava_osburn_masnari_1997, title={The effect of the elevated source drain doping profile on performance and reliability of deep submicron MOSFET's}, volume={44}, ISSN={["0018-9383"]}, DOI={10.1109/16.622606}, abstractNote={Deep submicron NMOSFETs with elevated source/drain (ESD) were fabricated using self-aligned selective epitaxial deposition and engineered ion implanted profiles in the elevated layers, Deeper source/drain (S/D) junctions give rise to improved drive current over shallower profiles when the same spacer thickness and LDD doping level are used, Shallower junctions, especially with the heavily-doped S/D residing in the elevated layer, give better immunity to drain-induced-barrier lowering (DLBL) and bulk punchthrough. Tradeoffs between short-channel behavior and drive current with regard to S/D junction depth and spacer thickness were further studied using process/device simulations to cover a broader range of structure parameters. Despite the existence of epi facets along the sidewall spacers, the elevated S/D could be used as a sacrificial layer for silicidation, without degradation of the low-leakage junctions. The effects of the elevated S/D doping profile on substrate current and hot-electron-induced degradation were measured and analyzed. The simulated results were used, for the first time, to define the range of spacer thickness and LDD doses that are required in order for the lightly-doped region in the elevated S/D to effectively suppress the lateral electric field.}, number={9}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Sun, JJ and Bartholomew, RF and Bellur, K and Srivastava, A and Osburn, CM and Masnari, NA}, year={1997}, month={Sep}, pages={1491–1498} }
 @article{sun_bartholomew_bellur_oneil_srivastava_violette_ozturk_osburn_masnari_1996, title={Sub-half micron elevated source/drain NMOSFETs by low temperature selective epitaxial deposition}, volume={429}, ISBN={["1-55899-332-0"]}, ISSN={["0272-9172"]}, DOI={10.1557/proc-429-343}, abstractNote={Abstract}, journal={RAPID THERMAL AND INTEGRATED PROCESSING V}, author={Sun, J and Bartholomew, RF and Bellur, K and ONeil, PA and Srivastava, A and Violette, KE and Ozturk, MC and Osburn, CM and Masnari, NA}, year={1996}, pages={343–347} }